Communication interfaces
A3M39SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, March 2022
Data Sheet: Technical Data
17
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33
Figure 6. SPI instruction sets diagram
SPI instruction set information:
•
R/W read = 1, write = 0
•
N1, N0
o
2’b00 1 byte
o
2’b01 2 bytes
o
2’b10 3 bytes
o
2’b11 4 bytes
•
A4, A3, A2, A1, A0 decode for address 0–15
•
MSB sent first, LSB last
9.2 I
2
C
The A3M39SL039I follows the I
2
C protocol standard. It supports I
2
C fast mode with a bit rate up to 400 Kbit/s. It also supports
I
2
C standard mode with bit rate up to 100 Kbit/s.
9.2.1 I
2
C addressing
The two external tri-state address pins A0 and A1 use 5 V logic levels and are decoded into 7-bit I
2
C addresses as shown
. The three LSBs of the 7-bit address are set via the A0 and A1 pins. The four MSBs are the base address, which
is fixed at 1000.
Table 17. I
2
C 7-bit address assignment
A1
A0
I
2
C 7-Bit Address
0
0
Not Translated
0
Z
1000 000
0
1
1000 001
Z
0
1000 010
Z
Z
1000 011
Z
1
1000 100
1
0
1000 101
1
Z
1000 110
1
1
1000 111
