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APPENDIX II
Post BIOS Beep Code
Number of Beeps
Description
1
Memory refresh timer error.
2
Parity error in base memory (first 64KB block)
3
Base memory read/write test error
4
Motherboard timer not operational
5
Processor error
6
8042 Gate A20 test error (cannot switch to protected mode)
7
General exception error (processor exception interrupt error)
8
Display memory error (system video adapter)
9
AMIBIOS ROM checksum error
10
CMOS shutdown register read/write error
11
Cache memory test failed
Debug Port Post Code
Bootblock Initialization Code Checkpoints
The Bootblock initialization code sets up the chipset, memory and other components
before system memory is available. The following table describes the type of
checkpoints that may occur during the bootblock initialization portion of the BIOS
1
:
Checkpoint
Description
Before D0
If boot block debugger is enabled, CPU cache-as-RAM functionality is
enabled at this point. Stack will be enabled from this point.
D0
Early Boot Strap Processor (BSP) initialization like microcode update,
frequency and other CPU critical initialization. Early chipset initialization is
done.
D1
Early super I/O initialization is done including RTC and keyboard controller.
Serial port is enabled at this point if needed for debugging. NMI is disabled.
Perform keyboard controller BAT test. Save power-on CPUID value in scratch
CMOS. Go to flat mode with 4GB limit and GA20 enabled.
D2
Verify the boot block checksum. System will hang here if checksum is bad.
D3
Disable CACHE before memory detection. Execute full memory sizing
module. If memory sizing module not executed, start memory refresh and
do memory sizing in Boot block code. Do additional chipset initialization.
Re-enable CACHE. Verify that flat mode is enabled.
D4
Test base 512KB memory. Adjust policies and cache first 8MB. Set stack.
D5
given to it. BIOS now executes out of RAM. Copies compressed boot block
