nvent Schroff 14579-040, Руководство пользователя

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14579-040 (PXIe System)
R1.5, January 2021 18 Slot PXIe Backplane (23007-518) 5
3 18 Slot PXIe Backplane (23007-518)
The PXIe backplane provides:
• 1 PXIe system slot
• 1 PXIe timing slot
• 16 PXIe Hybrid slots
- accepting CompactPCI, PXI, CompactPCI Express, and PXIe modules
• 2 PCIe-to-PCI high performance bridges
- utilize a single PCI segment for the hybrid slots
- designed to the PCI Express-to-PCI Bridge Specification 1.0 that enables applications to
migrate legacy parallel PCI bus interfaces to the advanced serial PCI Express
- each bridge is equipped with a single lane PCI Express port and a parallel bus segment
supporting the conventional PCI operation for up to eight PCI peripheral devices con-
currently.
- Primary Bus: x1 PCI Express Base Specification R1.1 compliant
- Secondary Bus: 33 MHz/32 bit PCI Local Bus Specification R3.0 compliant
• All PXIe hybrid slots with 32 bit 33 MHz PCI interface.
• 1 PXIe clock module
- generates and controls PXI specific high accuracy clocks and trigger signals.
• 4 ultra-high performance PCIe switches that operates with up to Gen 3 speeds.
• All PXIe hybrid and the timing slots have an x4 PCIe link providing a maximum data band-
width of 4 GB/s each.