Numark MP103USB, Руководство по разборке

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A A
Check REV Description
Title:
Size
A2
Number Revision
Date :
File Name:
Sheet of
Design By :
DATE Design Approval
2011/01/21
V02
MAIN- DSP&4M SRAM
NCR8C - TWPC10C03001
4 4
P2 P4 P6 P8
P9
R
5
3
0
P10
R
5
7
1
0
K
R
6
0
1
0
K
R
4
2
0
R
4
4
1
0
0
R
4
6
1
0
0
R
4
8
1
0
0
R
5
0
1
0
0
R
5
2
1
0
0
R
5
5
1
0
0
R78
1K 1%
TMS
R28 0
R26 100
R21 100
R19 0
R17 100
R14 0
R12 100
C4 0.1uF
C31 0.1uF
C30 0.1uF
C29 0.1uF
C28 0.1uF
C27 0.1uF
R65 10K
C37 0.01uF
C35 0.01uF
R67 10K
R66
10K
R79 2K 1%
C43 0.1uF
C41 0.1uF
C40 0.1uF
C39 0.1uF
R83 100
R89 10
R6 10K
S3.3V
C1 0.1uF
S3.3V
S3.3V
R36 10K
R29 0
R27 0
C6 0.1uF
R25 100
R24 100
R22 100
C5 0.1uF
R20 100
R18 100
R16 100
R13 0
P3 P5 P7
R
5
9
1
0
K
R
6
1
1
0
K
S3.3V
R62
1M
C21 22pF/50V
C20 22pF/50V
R63 0
R64 100K
C33
0.1uF
C36 0.1uF
C34 0.1uF
S3.3V
S3.3V
S3.3V
C47
0.01uF
C42 0.1uF
S3.3V
R82 0
S3.3V
C46
0.1uF
R80 0(DNS)
S3.3V
C49
0.01uF
C50
0.01uF
C51
0.01uF
C53
0.01uF
C55 0.1uF
C54 0.1uF
R3
10K
R2
10K
S3.3V
C
9
0
.1
u
F
R
4
3
1
0
0
R
3
7
1
0
K
C
1
1
0
.1
u
F
C
1
3
0
.1
u
F
C
1
2
0
.1
u
F
R
4
9
1
0
0
R
4
7
1
0
0
R
4
5
1
0
0
R
5
6
1
0
0
R
5
4
1
0
0
R
5
1
1
0
0
C
1
5
0
.1
u
F
C
1
6
0
.1
u
F
C
1
7
0
.1
u
F
C
1
4
0
.1
u
F
C
2
3
0
.1
u
F
C
2
2
0
.1
u
F
POK
3
FB
6
VIN
1
VOUT
8
VIN
2
EN
4
GND
5
VOUT
7
IC5
AP7165
S3.3V
C45
0.1uF
R
8
4
1
0
K
R
8
5
1
0
K
R
8
6
1
0
K
R
8
7
1
0
K
TDO
For the burn flash memory the use.
R10 100
R8 10K
R76 10K
R75 100
R73 10K
R71 10K
R70 100
C3
0.1uF
TDI
S3.3V
TCK
6 3 8 7 4 5 2 1
TE5
R9 100
R1 100
C2
0.1uF
X1
11.2896MHz
S3.3V
C48
0.01uF
R77 100
R74 10K
R72 100
R69 10K
C52
0.01uF
Core-1 :
Mode4 (Boot via SHI Master)
Mode DCBA = 0101h
R80 => NC
5
2
6
4
3
1
TE4
WP
3
SCLK
6
CS
1
VCC
8
GND
4
DO
2
DIN
5
Reset
7
IC1
ICA25L080-F
C
1
0
0
.1
u
F
P1
C
1
8
0
.1
u
F
C
1
9
0
.1
u
F
1Y
3
2A
4
2B
5
2Y
6
GND
7
1A
1
1B
2
4A
12
4Y
11
3B
10
3A
9
3Y
8
VCC
14
4B
13
IC7
74HC08
1Y
3
2A
4
2B
5
2Y
6
GND
7
1A
1
1B
2
4A
12
4Y
11
3B
10
3A
9
3Y
8
VCC
14
4B
13
IC6
74HC08
Core 0 :
Mode5 (Boot via Core 1)
Mode DCBA = 0100h
R82 => OR
Q1
DTC124EM
KEEP it length equals address + data line langth for timing delay.
*. Q5 = A10 ,A13 NO USE LACTH.
ICDSPB56724AG
(DSPB56724AG-1.2V)
AP7165 (Max 600mA)
FB : Vout = 0.8v(1+R78/R79)
1.2v = 0.8v(1+1K/2K)
Q2
6
D2
7
GND
10
Q1
5
D3
8
Q3
9
OE
1
Q0
2
LE
11
Q4
12
D4
13
D5
14
Q5
15
Q6
16
Q7
19
D0
3
D1
4
D6
17
D7
18
VCC
20
IC3
74HC373A
DSP56724 - Module board
Q2
6
D2
7
GND
10
Q1
5
D3
8
Q3
9
OE
1
Q0
2
LE
11
Q4
12
D4
13
D5
14
Q5
15
Q6
16
Q7
19
D0
3
D1
4
D6
17
D7
18
VCC
20
IC4
74HC373A
IO
_
V
D
D
1
0
7
P
IN
T
/N
M
I
1
0
5
T
D
I
1
0
3
T
M
S
1
0
1
C
O
R
E
_
V
D
D
9
5
S
C
K
R
/P
C
0
9
3
S
C
K
T
/P
C
3
9
1
S
D
O
3
/S
D
I2
/P
C
8
8
7
S
D
O
5
/S
D
I0
/P
C
6
8
5
S
P
D
IF
IN
1
8
3
IO
_
V
D
D
8
1
X
T
A
L
7
9
P
L
L
D
_
G
N
D
7
7
P
L
L
A
_
G
N
D
7
5
P
L
L
P
_
V
D
D
7
3
S
D
O
3
_
1
/S
D
I2
_
1
/P
E
8
9
9
S
D
O
5
_
1
/S
D
I0
_
1
/P
E
6
9
7
H
C
K
T
/S
T
C
L
K
/P
C
5
8
9
MODA0/IRQA
143
MODC0/PLOCK
141
FSR_3/PE1_1
139
FST_3/PE4_1
135
IO_GND
133
CORE_GND
131
MODA1/IRQC
129
MODC1/NMI
127
SS/HA2
117
SCK/SCL
115
MISO/SDA
113
RESET
111
CORD_VDD
109
C
O
R
E
_
V
D
D
1
SCAN
144
MODD0/PG1
140
MODB0/IRQB
142
MODB1/IRQD
128
CORE_VDD
130
IO_VDD
132
MODD1/PG2
126
SS_1/HA2_1
112
MOSI/HA0
114
HREQ/PH4
116
IO
_
G
N
D
1
0
8
CORD_GND
110
L
C
S
0
4
L
C
S
1
5
L
C
S
2
6
L
C
S
3
7
L
C
S
4
8
L
C
S
5
9
T
C
K
1
0
2
T
D
O
1
0
4
W
D
T
1
0
6
IO
_
V
D
D
1
2
IO
_
G
N
D
1
3
C
O
R
D
_
V
D
D
1
4
C
O
D
E
_
G
N
D
1
5
L
W
E
1
6
L
O
E
1
7
H
C
K
R
/P
C
2
9
2
F
S
R
/P
C
1
9
4
C
O
R
D
_
G
N
D
9
6
L
C
K
E
2
0
L
C
L
K
2
1
L
B
C
T
L
2
2
L
S
D
W
E
2
3
L
S
D
C
A
S
2
4
L
G
T
A
2
5
S
P
D
IF
O
U
T
1
8
4
F
S
T
/P
C
4
9
0
S
D
O
4
/S
D
I1
/P
C
7
8
6
S
D
O
2
/S
D
I3
/P
C
9
8
8
L
A
2
2
8
IO
_
V
D
D
2
9
IO
_
G
N
D
3
0
P
L
L
P
1
_
V
D
D
3
2
P
L
L
P
1
_
G
N
D
3
1
P
L
L
D
1
_
G
N
D
3
3
P
L
L
D
_
V
D
D
7
6
P
L
L
D
_
G
N
D
7
8
E
X
T
A
L
8
0
IO
_
G
N
D
8
2
P
L
L
A
1
_
V
D
D
3
6
LSYNC_IN
37
LAD22
40
LAD21
41
LAD20
42
LAD19
43
LAD18
44
LAD17
45
IO_VDD
48
IO_GND
49
LAD16
50
LAD15
51
LAD14
52
LAD13
53
LAD10
56
LAD9
57
IO_VDD
58
IO_GND
59
CORE_VDD
60
CORE_GND
61
LAD6
64
LAD5
65
LAD4
66
LAD3
67
LAD2
68
LAD1
69
IO_VDD
72 P
L
L
A
_
V
D
D
7
4
S
D
O
2
_
1
/S
D
I3
_
1
/P
E
9
1
0
0
S
D
O
4
_
1
/S
D
I1
_
1
/P
E
7
9
8
LSYNC_OUT
38
LAD23
39
CORE_VDD
46
CORD_GND
47
LAD12
54
LAD11
55
LAD8
62
LAD7
63
LAD0
70
IO_GND
71
C
O
R
E
_
G
N
D
2
L
A
L
E
3
L
C
S
6
1
0
L
C
S
7
1
1
L
G
P
L
5
1
8
L
S
D
A
1
0
1
9
L
A
0
2
6
L
A
1
2
7
P
L
L
D
1
_
V
D
D
3
4
P
L
L
A
1
_
G
N
D
3
5
HCKR_3/PE2_1
137
SDO2_2/SDI3_2/PC9_1
125
SDO4_2/SDI1_2/PC7_1
123
SDO2_3/SDI3_3/PE9_1
121
SDO4_3/SDI1_3/PE7_1
119
SCKT_3/PE3_1
136
SCKR_3/PE0_1
138
HCKT_3/PE5_1/STCLK
134
SDO3_3/SDI2_3_PE8_1
120
SDO5_2/SDI0_2/PC6_1
122
SDO3_2/SDI2_2/PC8_1
124
SDO5_3/SDI0_3/PE6_1
118
IC2
A3
26
A1
24
A10/AP
22
BA0
20
RAS
18
WE
16
VDD
14
VSSQ
12
DQ5
10
DQ4
8
VSSQ
6
DQ1
4
DQ0
2
A4
29
A6
31
A8
33
A11
35
CKE
37
UDQM
39
VSS
41
VDDQ
43
DQ10
45
DQ11
47
VDDQ
49
DQ14
51
DQ15
53
VDD
27
A2
25
A0
23
BA1
21
CS
19
CAS
17
LDQM
15
DQ7
13
DQ6
11
VDDQ
9
DQ3
7
DQ2
5
VDDQ
3
VDD
1
VSS
28
A5
30
A7
32
A9
34
NC
36
CLK
38
NC/RFU
40
DQ8
42
DQ9
44
VSSQ
46
DQ12
48
DQ13
50
VSSQ
52
VSS
54
IC8
ICM12L64164A-7T
A0
A0
A1
A1
A11
A11
A12
A12
A14
A14
A15
A15
A2
A2
A3
A3
A4
A4
A5
A5
A6
A6
A7
A7
A8
A8
A9
A9
DSP-RESET
HREQ/PH4
LAD1
LAD1
LAD10
LAD10
LAD11
LAD11
LAD11
LAD12
LAD12
LAD12
LAD13
LAD13
LAD14
LAD14
LAD14
LAD15
LAD15
LAD15
LAD16
LAD16
LAD17
LAD17
LAD18
LAD18
LAD19
LAD19
LAD2
LAD20
LAD20
LAD21
LAD21
LAD22
LAD22
LAD23
LAD23 LAD3
LAD3 LAD4
LAD4
LAD5
LAD5
LAD6
LAD6
LAD7
LAD7
LAD8
LAD8
LAD8
LAD9
LAD9
LAD9
LALE
LALE
L
A
L
E
LCKE
L
C
K
E
L
C
L
K
LCLK
L
C
S
7
LCS7
L
S
D
A
1
0
LSDA10
LSDCAS
L
S
D
C
A
S
LSDDQM
LSDDQM
L
S
D
D
Q
M
L
S
D
R
A
S
LSDRAS
L
S
D
W
E
LSDWE
MODA1
MODC1
SPI-CLK
SPI-MISO
SPI-MOSI
SGND
SGND
SGND
SGND
SGND
SGND
SGND
SGND
SGND
SGND
SGND
SGND
SGND
SGND
SGND
SGND
SGND
SGND
SGND
SGND
SGND SGND
SGND
SGND
SGND
Core Power
Core Power
R
4
1
1
0
0
R
4
0
1
0
0
R
3
9
1
0
0
R
3
8
1
0
0
R33 100
R34 100
R35 100
R5 10K
R7 10K
LAD2
LSYNC
LAD0
LAD0
LAD[0..23]
LAD[0..23]
(DNS)
DSP-RESET
MODA1
OTG-RESET
MODC1
SPI-CLK
SPI-MISO
SPI-MOSI
JOG-R
JOG-F
DAC-DIN
DAC-DM
DSP_RDY
DSP_INT
DAC-SCK
DAC-LRCK
DAC-BCK
DSP_CE
HREQ/PH4
OTG-INSERT
SUBSYQ/MODB1
WFCK/MODD1
OTG-DataRdy/MODA0
OTG-DataRdy/MODB0
OTG-DataErr/MODD0
DAC-MUTE
R4
330
Ω
R15 0
R30
0(DNS)
U
S
B
-D
4
U
S
B
-D
5
U
S
B
-D
6
U
S
B
-D
7
U
S
B
-D
3
U
S
B
-D
2
U
S
B
-D
1
U
S
B
-D
0
S
E
R
V
O
-D
C
K
S
E
R
V
O
-L
R
C
K
S
E
R
V
O
-D
O
U
T
A
S
E
R
V
O
-S
U
B
C
K
S
E
R
V
O
-S
U
B
D
A
T
A
O
T
G
_
C
L
K
Q2
DTC124EM
M_RST
SGND
SGND
WFCK
OTG-DataRdy/MODB0
OTG-DataRdy
SUBSYQ/MODB1
SUBSYQ
OTG-DataErr/MODD0
OTG-DataErr
WFCK/MODD1
OTG-RESET
DSP-RESET DSP-MODE
C57
1uF
R91
1K
SGND
OTG-DataRdy/MODA0
OTG-DataRdy
EC4
1
0
u
F
/1
6
V
EC5
1
0
u
F
/1
6
V
EC6
10uF/16V
EC3
47uF/16V
EC2
1
0
0
u
F
/1
6
V
EC1
2
2
0
u
F
/1
6
V
SPDIFOUT1_1
R90
4.7K
DSP
DSP Core Power Regulator
Serial (SPI) Serial (SPI) Flash Memory
DSP - Interrupt / Operating Mode Logical
4M*16BIT-MEMORY
ICYHFRC178
2011.01.21
1.ICK4S641632E>>ICM12L64164A-7T
2.
EC
NOTE