NuDAQ ACL-8112 Series, Руководство пользователя

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Registers Format
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4.9 D/A Output Register
The D/A converter will convert the D/A output register data to the analog
signal. The register data of the address Base + 4 and Base + 5 are used
for D/A channel 1, Base +6 and Base +7 are used for D/A channel 2.
Address : BASE + 4 & BASE + 5
Attribute: write only
Data Format: (for D/A Channel 1)
Bit 7 6 5 4 3 2 1 0
Base + 4 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
Base + 5 X X X X DA11 DA10 DA9 DA8
Address : BASE + 6 & BASE + 7
Attribute: write only
Data Format: (for D/A Channel 2)
Bit 7 6 5 4 3 2 1 0
Base + 6 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
Base + 7 X X X X DA11 DA10 DA9 DA8
DA0 is the LSB and DA11 is the MSB of the 12 bits data.
X: don't care
Note: The D/A registers are " double buffered " so that the D/A analog
output signals will not updated until the second ( high ) byte is
written. This can insure a single step transition when the D/A
conversion.
4.10 Internal Timer/Counter Register
Two counter of 8254 are used for periodically triggering th e A/D
conversion, the left one is left free for user applications. The 8254
occupies 4 I/O address locations in the ACL-8112 as shown blow. Users
can refer to NEC's or Intel's data sheet for a full description of the 8254
features, condensed information is specified in Appendix B.
Address : BASE + 0 ~ BASE + 3
Attribute: read / write
Data Format:
Base + 0 Counter 0 Register ( R/W)
Base + 1 Counter 1 Register ( R/W)