
NT4N39AA CP Pentium IV Card
Page 187 of 906
Circuit Card
Description and Installation
double pumped address bus (addresses running at 2*100 MHz = 200 MHz) is
32 bit wide supporting an address range of up to 4 GBytes. The processor
voltage specification is compliant with IMVP IV specification.
Memory
CP PIV memory uses DDR SDRAM technology. The CP PIV provides a
maximum of two GBytes using two vertical DIMM sockets to install
off-the-shelf DIMM modules. CP PIV only supports DDR SDRAM DIMM
memory with a supply voltage of +2.5V.
The memory data path is 72-bit wide. The Intel 855GME Host Bridge
supports 128 MByte, 256 MByte and 512 Mbyte SDRAM technologies with
a maximum ROW page size of 16 Kbytes and CAS latency of 2 or 2.5. The
maximum height of the DIMM modules possible on CP PIV is one inch or
25.4 mm.
The DDR interface runs at 100 MHz synchronously to the front side bus
frequency. The SPD (Serial Presents Detect) -SROM available on DIMM
modules provide all necessary information (speed, size, and type) to the
boot-up software. The SPD-SROM can be read via SMBUS connected to the
Intel Hance Rapids South Bridge.
Front panel connector pin assignments
COM1 and COM2 ports
The physical interface for the COM1 and COM2 ports to the front panel is
through a stacked dual Male DB9 Connector. The corresponding pin details
are shown in Table 72.
Table 72
COM1 and COM2 pin assignments
Pin number
Pin name
1
DCD
2
RXD
3
TXD
Содержание Circuit Card
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Страница 906: ...Page 906 of 906 Appendix A LAPB Data Link Control protocol 553 3001 211 Standard 3 00 August 2005...
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