Nokia NHM-7 series, Руководство по обслуживанию

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NHM–7
System Module & UI
PAMS Technical Documentation
Page 34 Issue 1 10/2001
Nokia Corporation
Frequency synthesizers
VCO frequency is locked with PLL into stable frequency source, which is
a VCTCXO–module ( voltage controlled temperature compensated crystal
oscillator ). VCTCXO is running at 26 MHz. Temperature drifting is con-
trolled with AFC ( automatic frequency control ) voltage. VCTCXO is
locked into frequency of the base station. AFC is generated by baseband
with a 11 bit conventional DAC. 13MHz VCTCXO can also be used if mul-
tislot operations is not needed. If more than 1(RX)+1(TX) slot is wanted
settling times have to be less than 300us from channel to channel. This
can be achieved when PLL loopbandwith is ~35kHz. Noise coming from
the loop and noise from dividers (20*logN) increases rms phase error
over 3 degrees which is the maximum for synthesizer.
VCO
CHARGE
PUMP
PHASE
DET.
M
R
f_out
LP
Kvco
Kd
M = A(P+1) + (N–A)P=
f
ref
f_out /M
26 MHz frequency reference
= NP+A
AFC–controlled VCTCXO
PLL is located in HAGAR RF–IC and is controlled via serial RFBus. There
is 64/65 (P/P+1) prescaler, N– and A–divider, reference divider, phase de-
tector and charge pump for the external loop filter. SHF local signal, gen-
erated by a VCO–module ( VCO = voltage controlled oscillator ), is fed
thru 180deg balanced phase shifter to prescaler. Prescaler is a dual mo-
dulus divider. Output of the prescaler is fed to N– and A–divider, which
produce the input to phase detector. Phase detector compares this signal
to reference signal (400kHz), which is divided with reference divider from
VCTCXO output. Output of the phase detector is connected into charge
pump, which charges or discharges integrator capacitor in the loop filter
depending on the phase of the measured frequency compared to refer-
ence frequency.
Loop filter filters out comparison pulses of phase detector and generates
DC control voltage to VCO. Loop filter defines step response of the PLL (
settling time ) and effects to stability of the loop, that’s why integrator ca-
pacitor has a resistor for phase compensation. Other filter components
are for sideband rejection. Dividers are controlled via serial bus. RFBus-
Data is for data, RFBusClk is serial clock for the bus and RFBusEna1X is
a latch enable, which stores new data into dividers.
LO–signal is generated by SHF VCO module. VCO has double frequency
in GSM1800 and x 4 frequency in EGSM compared to actual RF channel