A-8
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Appendix A
Specifications
External 10 MHz Reference Out (BNC on rear panel of chassis)
Accuracy
±25 ppm max (guaranteed over the operating
temperature range)
Maximum jitter
5 ps RMS phase-jitter (10 Hz to 1 MHz range)
Output amplitude
1 V
PP
±20% square-wave into 50
Ω
2 V
PP
unloaded
Output impedance
50
Ω
±5
Ω
External Clock Source
Frequency
10 MHz ±100 PPM
Input amplitude
Rear panel BNC
200 mV
PP
to 5 V
PP
square-wave or sine-wave
System timing slot PXI_CLK10_IN
5 V or 3.3 V TTL signal
Rear panel BNC input impedance
50
Ω
±5
Ω
Maximum jitter introducedby backplane
1 ps RMS phase-jitter (10 Hz to1 MHz range)
PXIe_SYNC_CTRL
V
IH
2.0 to 5.5 V
V
IL
0 to 0.8 V
PXI Star Trigger
Maximum slot-to-slot skew
250 ps
Backplane characteristic impedance
65
Ω
±10%
Note
For PXI slot to PXI Star mapping refer to the
System Timing Slot
section of
Chapter 1,
Getting Started
.
For other specifications refer to the
PXI-1 Hardware Specification
.
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