NI ELVIS RIO, Руководство пользователя

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Figure 2. NI ELVIS RIO CM Hardware Block Diagram
Processor (LabVIEW RT)
FPGA (LabVIEW FPGA)
MXP A/B
(x2)
+3.3 V
UART
4
AI
2
AO
16 16
DIO
DDR3
Nonvolatile
Memory
Reset
Button
USB Device
Port
USB Host
Port
Xilinx Zynq-7010
User
LEDs
+5 V
Button0
Watchdog
Status
LED
MXP Connector Pinout
A
O0
A
O1
A
GND
DGND
U
AR
T.RX
DGND
U
AR
T.TX
DGND
DIO11 / ENC
.A
DGND
DIO12 / ENC
.B
DGND DIO13 DGND DGND
DIO14 / I2C
.SCL
DIO15 / I2C
.SD
A
+5V AI1 AI3 AI2 DIO1 DIO2 DIO3 DIO4 AI0 DIO0 DIO5 / SPI.CLK DIO6 / SPI.MISO DIO7 / SPI.MOSI DIO8 / PWM0 DIO9 / PWM1 DIO10 / PWM2 +3.3V
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
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