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31
NDiS B325 Series User Manual
Appendix A: Watchdog
a
PPendIx
a: W
atChdog
Watchdog Timer Control Register (Index=71h, Default=00h)
Bit
Description
7
WDT is reset upon a CIR interrupt.
6
WDT is reset upon a KBC (Mouse) interrupt.
5
WDT is reset upon a KBC (Keyboard) interrupt.
4
WDT Output through RSTCONOUT (pulse) Enable
1: Enable
0: Disable
3
External CLK_IN Select
0: CLKIN
1: PCICLK
2
Reserved
1
Force Time-out
This bit is self-cleared.
0
WDT Status
1: WDT value is equal to 0.
0: WDT value is not equal to 0.
SMI# Control Register 2 (Index=F1h, Default=00h)
Bit
Description
7
Reserved
6
0: Edge trigger
1: Level trigger
5-3
Reserved
2
This bit is to enable the generation of a SMI# due to WDT’s IRQ (EN_WDT).
1
This bit is to enable the generation of a SMI# due to CIR’s IRQ (EN_CIR).
0
This bit is to enable the generation of a SMI# due to PBD’s IRQ (EN_PBD).
SMI# Status Register 2 (Index=F3h, Default=00h)
This register is used to read the status of SMI# inputs.
Bit
Description
7-6
Panel Button De-bounce Status 1-0
Writing 1 will reset the status.
0: None detected
1: Detected
5-4
Reserved
3
Reserved
2
WDT’s IRQ
1
CIR’s IRQ
0
PBD’s IRQ
