Copyright © 2012 NEXCOM International Co., Ltd. All Rights Reserved.
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NDiS 542 User Manual
Appendix C: Watchdog Timer
Appendix C: Watchdog Timer
NDiS 542 features a watchdog timer that resets the CPU or generates
an interrupt if the processor stops operating for any reason. This
feature ensures system reliability in industrial standalone or unmanned
environments.
Watchdog Timer Control Register
(Index=71h, Default=00h)
Watchdog Timer Control Register
(Index=72h, Default=001s0000b)
Bit
Description
7
WDT is reset upon a CIR interrupt
6
WDT is reset upon a KBC (mouse) interrupt.
5
WDT is reset upon a KBC (keyboard) interrupt.
4
WDT is reset upon a read or a write to the Game
Port base address.
3-2
Reserved
1
Force Time-out. This bit is self-clearing.
WDT Status
0
1: WDT value reaches 0.
0: WDT value is not 0.
Bit
Description
7
WDT Time-out value select 1
1: Second
0:Minute
6
WDT output through KRST (pulse) Enable
1: Enable
0: Disable
5
WDT Time-Out Value Extra Select
1: 64ms x WDT Timer-out value (default=4s)
0: Determined by WDT Time-out value select 1 (bit 7
of this register)
4
WDT Output through PWEGD Enable
1: Enable
0: Disable
During LRESET# this bit is selected by JP2 power-on
strapping option.
3-0
Interrupt level Select for WDT.
