Nexcom EBC575 Series, Руководство пользователя

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41 Chapter 4 EBC575 User’s Manual
Figure 4-5: BIOS – Advanced Chipset Features
DRAM Timing Selectable
The choices are: Manual, and By SPD. The option “By SPD” enables the system to automatically set the
SDRAM timing by Serial Presence Detect (SPD). SPD is an EEPROM chip on the DIMM module that stores
information about the memory chips it contains, including size, speed, voltage, row and column addresses,
and manufacturer. Select “Manual” allows users manually set the following four timing parameters for the
system memory.
CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends on the DRAM
timing. Do not reset this field from the default value specified by the system designer. The choices are: 1.5,
2, 2.5, 3.
Active to Precharge Delay
This item controls the number of DRAM clocks for TRAS. The choices: 5, 6, 7.
DRAM RAS# to CAS# Delay
This field let you insert a timing delay between the CAS and RAS strobe signals, used when DRAM is written
to, read from, or refreshed. Fast gives faster performance; and slow gives more stable performance. This
field applies only when synchronous DRAM is installed in the system. The choices are: 2, 3.
DRAM RAS# Precharge
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before DRAM refresh, the
refresh may be incomplete and the DRAM may fail to retain data. Fast gives faster performance; and Slow
gives more stable performance. This field applies only when synchronous DRAM is installed in the system.
The choices are 2 and 3.
System BIOS cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in better system
performance. However, if any program writes to this memory area, a system error may result. The available
choices are Enabled, Disabled.