New Micros NMIY-0031, Руководство пользователя

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2 / 2 6 / 2 0 0 2 2 : 0 6 P M 2 / 2 6 / 2 0 0 2 3 5
N M I Y - 0 0 3 1 P R O G R A M M I N G
DATA PORTS
Two general purpose data ports are available. One port is an externally memory-mapped, latched
I/O port. The other is a raw (unprocessed) interface to processor Port 1.
L A T C H E D D A T A P O R T ( J 4 )
The twenty pins of J4 contain latched input and output. These lines are an augmented alternative
to the keypad inputs on J3. All eight lines of both the read and write latches are available. The
latched data port and keypad use the same data latches. Please see the keypad information below
for programming details on the latches.
R A W D A T A P O R T ( J 5 )
J5 gives the user access to Port 1 of the processor, timers 0 and 1, and interrupts 0 and 1..
Caution:
be certain that any load/source attached meets the specifications of the 8031 processor.
Port 1 pins can source/sink up to four LSTTL loads. Excessive loads or signals can result in
processor failure. 8031 data books give timer and interrupt programming information.
The CSX signal is a chip select that maps to FExx in data space for both read and write. The user
can use this 256 byte memory block as desired, i.e. for custom memory mapped devices. The
lower eight address bits are available on the VSC connectors as needed. RST is the master board
reset used throughout the board.
Data lines on J5 are very useful for external control. The interrupts can be used to signal when
particular services are needed from the processor. The timer outputs/counter inputs are useful
for checking time dependent processes. Also, the direct data inputs are useful for bit oriented
input/output. These are a few suggestions for using the direct input/output connections. See an
8031/51A data book for details on timer, counter, and interrupt programming.
KEYPAD I/F
The NMIY-0031 keypad is designed to be used with a matrix type keypad. A matrix keypad
works by shorting together the corresponding row and column lines when a key is pressed. To
detect a key press, the program writes a value to the column data lines with the output latch. The
value sent out has a zero bit in the position corresponding to the column to be examined. The
row values, are then latched and examined. Software must determine which row and which
column are activated before the operator releases the key. Any column not pressed will return a
row value of FF. The column pressed will return a row value with a positional zero bit indicating
which key is pressed. Valid returns are FF, FE, FD, FB, and F7. See the “Program Segments”
chapter for examples.
The column-data latch address is FFFC. Writing to this address causes the data to be latched.
This latched byte is then available at J4 and the lower five bits (D4 - D0) are presented to the
column inputs of the keypad. The row data latch address is FFFC. Reading FFFC latches the
data of the four keypad row lines (D3 - D0). Until known data is latched onto the columns,
returned row data will be meaningless. See “Program Segments” for examples.