DWC-HD
Rev.
2
3 Description
3.1 Data
path
The HD/SD-SDI input selected from the optical or electrical input is equalized, re-clocked and
de-serialized and transferred to a processing unit (FPGA). In the FPGA the signal is sent
through a
de-glitcher
that cleans up erroneous video lines, for instance due to switching.
After the de-glitcher the video is sent to the
Audio de-embedders
, where audio is split from
the video.
3.1.1 Audio data path
The 16 audio channels coming out of the de-embedder are bundled
in pairs
and sent to an
audio store buffer. After a user specified delay the audio is fetched from the audio store
buffer and sent to an
Audio Cross Point.
The 10 audio outputs from the Audio Cross Point
can be any pair of audio channels de-embedded from the incoming video stream, a
generated 1 kHz sine, or a generated
black sound
(a legal audio stream with silence only).
As part of the audio cross point, missing output pairs can be replaced with generated fallback
signals. From the cross point outputs each stereo pair enters an
Audio Processing Block
where channels can be processed or rearranged within each channel pair. Finally, eight
stereo pairs are routed to the
Audio Embedder
and the two remaining pairs are sent to the
audio DAC and the AES out, respectively.
3.1.2 When down-converting HD video
The video is routed to a
Scaling block
and the resulting SD video is passed to a
Frame
synchronizer block
. If video is missing, an internal video generator can be switched in as a
fallback source. The video then passes through a
Video processing block
with an integrated
Legalizer
, before entering an
EDH processing block
where the user can select to insert
updated EDH flags. Although audio is re-embedded before the video processing block, the
video processing and EDH processing blocks will not manipulate the audio data.
After passing the
EDH block
, the video stream with embedded audio is sent in parallel out of
the FPGA and into a serializer that re-clocks the data and sends the SDI to a buffered output
switch.
The buffered output switch can be viewed as 3 simple switches, each selecting between the
equalized and re-clocked output (
Through
mode) and the down-converted output (
Processed
mode). The output of the first two switches are sent to two paired (inverting and non-
inverting) digital outputs, whereas output of the third switch is sent to the onboard video
DAC.
3.1.3 When frame synchronizing SD video
The video data path when operating as an SD frame synchronizer is conceptually the same
as when down-converting, except that the Scaling block is not needed, placing the Frame
synchronizer block directly after the de-glitcher.
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