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NM500 Manual

18

Write taking two cycles:

REG LCOMP (0x02)

Remark: When the DS signal is asserted the DATA bus must be set the value to write (i.e. 0x000b). It is then
switched to a tri-state mode (i.e. 0xFFFF) during a search and sort between the firing neurons so they can
determine if the input vector is identified (ID_l), uncertain (UNC_l) or unknown.

Read taking sixteen cycles:

REG DIST (0x03)

4.2

LEARN A VECTOR

In the example below, a vector of 8 components is learned. The resolution of the diagram does not allow for the
display of the DATA values, but this is not important for understanding the timing constraints of the chip.

The sequence of instructions consists of 7 Write COMP, 1 Write LCOMP, and 1 Write CAT.

When REG is equal to 01, each DS pulse triggers a Write COMP lasting one cycle of G_CLK. The RDY signal has the
same duration as the DS only shifted by one half clock cycle.

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Содержание NM500

Страница 1: ...NM500 User s Manual NeuroMem chip 576 neurons Version 1 6 3 Revised 04 18 2019 ...

Страница 2: ...m General Vision for the NeuroMem technology This manual is published and copyrighted by General Vision Inc All rights reserved For information about the NeuroMem digital neuromorphic technology refer to the General Vision web site at www general vision com and in particular the NeuroMem Technology Reference Guide ...

Страница 3: ...16 3 2 7 UNC_ 16 4 Typical Timings Constraints 17 4 1 Timings 17 4 2 Learn a vector 18 4 3 Recognize a vector 19 5 Interconnecting chips 20 5 1 Counting the neurons in a chain of unknown length 20 5 2 Verifying the proper interconnectivity of the entire chain 20 5 3 If a chain has more than 65535 neurons 21 5 4 Single or multiple chains of neurons 21 6 Pinout 22 7 Mechanical specifications 25 8 El...

Страница 4: ...mation which can be read from a firing neuron includes its distance category and neuron identifier If the response of several or all firing neurons is polled this data can be consolidated to make a more sophisticated decision weighing the cost of uncertainty or else 1 1 ARCHITECTURE The NM500 chip has a unique homogeneous architecture Chain of identical neurons daisy chained Intra Chip and Inter C...

Страница 5: ...ised or unsupervised Distance output given the distance between an input pattern and the pattern stored in the Memory of the neuron AIF Active Influence Field auto adjusted by the neuron MINIF Minimum influence field of the neuron Identifier Position of the neuron in the chain of neurons available A neuron is said committed when it stores a pattern to its memory along with a category with a value ...

Страница 6: ...0B RW 0x0001 MINIF Minimum Influence Field 0x06 RW RW 0x0002 MAXIF Maximum Influence Field 0x07 RW 0x4000 NCR Neuron Context Register 0x00 RW 0x0001 COMP Component 0x01 W RW 0x0000 LCOMP Last Component 0x02 W 0x0000 INDEXCOMP Component index 0x03 W W 0x0000 DIST Distance register 0x03 R R 0xFFFF CAT Category register 0x04 RW RW 0xFFFF AIF Active Influence Field 0x05 RW 0x4000 NID Neuron Identifier...

Страница 7: ...g will only create a single neuron per new category Writing Bit 4 to 1 switches the chain of neuron to SR mode and points directly to the RTL neuron GCR Norm Context and also partial identifier of the RTL neuron Bit 6 0 Context Bit 7 Lsup Norm Bit 23 16 Identifier 23 16 Global Context assigned to all neurons not already committed If the Norm is not set to LSUP the default is the L1 Norn or Manhatt...

Страница 8: ...ite moves to the next INDEXCOMP of the pointed neuron LCOMP Last Component Bit 15 8 unused Bit 7 0 byte component Write LCOMP stores the component at the current INDEXCOMP value and updates the DIST register of the committed neurons with NCR GCR and also of the RTL neuron INDEXCOMP is set to 0 The ID_ and UNC_ lines are updated to report the recognition status If ID_ line is low the identified cat...

Страница 9: ... influence fields Read CAT returns the category of the top firing neuron CAT 0xFFFF means that there are no more firing neurons Must be read after the DIST register except if the ID_ line is low and the NID register does not need to be read after the CAT register Category of the pointed neuron Read or Write CAT automatically moves to the next neuron index in the chain AIF Active Influence Field Th...

Страница 10: ...ual 1 otherwise 0 RESET CHAIN N A Points to the first neuron of the chain TESTCOMP 2 For all committed neurons write their component pointed by the current INDEXCOMP with the same input value Refer to paragraph below for use model TESTCAT 2 Write the same category to all the neurons Useful for test routines to commit all neurons in one clock cycle Refer to paragraph below for use model 1 If the co...

Страница 11: ...are snooping commands meaning they are making open collector bus mixing The release of the DATA lines as well as the ID_ and UNC_ lines after the fall of the DS signal is critical so they can snoop properly The following table reports the number of clock cycles cc necessary to read and write the registers of the chip The cycles are counted from the first rising edge of the system clock upon the re...

Страница 12: ...dcast a vector of Length L L 3 7 3 µs 14 3 µs Learn a vector of length L L 3 18 7 9 µs 15 4 µs Status of a vector of length L L 3 1 7 4 µs 14 4 µs Best match of a vector of length L L 3 37 8 3 µs 16 2 µs Get the K top match of a vector of length L L 3 K 37 9 1 µs 17 8 µs Save N neurons 4 N 260 4 27 ms 8 3 ms Restore N neurons 4 N 260 4 27 ms 8 3 ms ...

Страница 13: ... supply line 3 3 v GND Ground line DCI Input Daisy Chain In DCO Output Daisy Chain Out Clock and Reset G_CLK Input System clock G_RESET_ Input Hardware reset CS_ Input Enable chip activity NeuroMem bus DS Input Data strobe line R W_ Input Read Write REG 0 3 Input Register DATA 0 15 Bidir Data Neuron output lines ID_ Bidir Identified_low line UNC_ Bidir Uncertain_low line RDY Output Ready line ...

Страница 14: ...pull CS_ down and let the system clock pass through must be accurate It must be pulled down on a negative edge of the clock when the external data strobe DS is high It must be released on the negative edge of the clock following the rise of the RDY signal at the earliest 3 1 4 DCI Until the DCI line of a chip is high its neurons are idle As soon as the DCI line rises the neurons of the chip become...

Страница 15: ...l of all the neurons in the chain and indicating that neurons have identified the last vector and that these neurons are all in agreement for its classification UNC_ Control line mixing the UNC_ output signal of all the neurons in the chain and indicating that neurons have identified the last vector but disagree with its classification This line is an in out line because used as an input during th...

Страница 16: ...ecognizing the last input vector are all in agreement and return the same category This line is updated each time the last component of a vector is broadcasted to the neurons either through a Write LCOMP command The actual update occurs at the 3rd negative edge of the clock during the execution of the Write LCOMP The ID_ line is released at the next Write COMP The ID_ line is also continuously lat...

Страница 17: ...before the positive edge of G Clock The hold time must be at least 5 nanoseconds after the positive edge of the clock The neurons pull down their RDY line when the DS rises and hold it down for the duration of the command Upon completion the RDY line is pulled back up on the positive edge of the system clock The CS_ signal must be pulled down at the latest when the DS signal rises and it can be pu...

Страница 18: ...nown Read taking sixteen cycles REG DIST 0x03 4 2 LEARN A VECTOR In the example below a vector of 8 components is learned The resolution of the diagram does not allow for the display of the DATA values but this is not important for understanding the timing constraints of the chip The sequence of instructions consists of 7 Write COMP 1 Write LCOMP and 1 Write CAT When REG is equal to 01 each DS pul...

Страница 19: ...wn at the last negative edge of G_CLK before RDY is pulled back up This indicates that the input vector is recognized by more than one neuron and that different categories are identified When REG is equal to 03 and RW_l remains high the DS pulse triggers a Read DIST The RDY signal is pulled down for 18 cycles which is the duration of the Search and Sort looking for the firing neuron with the small...

Страница 20: ... to do so will prevent the proper execution of commands interconnecting all the neurons together through the bi directional lines of DATA ID_ and UNC_ 5 1 COUNTING THE NEURONS IN A CHAIN OF UNKNOWN LENGTH Write NSR 0x10 Set the SR mode Write TESTCAT Value Commit all the neurons with a same category value Write RESETCHAIN Point to the 1st neuron in chain Ncount 0 Do Loop o Read CAT cat o Ncount Unt...

Страница 21: ...chain 65535 neurons If chain 65535 neurons Report the number of committed neurons ncount Read NCOUNT N1 Read GCR N2 Read NCOUNT ncount N1 15 8 0xFFFF N2 15 0 Report the identifier of the next closest firing neuron nid Read NID N1 Read NCR 7 0 the bit reporting the identifier are shifted to the lower byte at the time of the readout The context information is dropped N2 Read NID 15 0 nid N1 15 8 0xF...

Страница 22: ...rons or 2 separate chains of neurons 6 PINOUT Signal Schematic Case Type DCI E7 E7 Input DCO F2 F2 Output D00 F2 F2 BiDir D01 E1 E1 BiDir D02 E2 E2 BiDir D03 D1 D1 BiDir D04 C2 C2 BiDir D05 C1 C1 BiDir D06 A2 A2 BiDir D07 B2 B2 BiDir D08 A3 A3 BiDir D09 B3 B3 BiDir D10 A4 A4 BiDir D11 B4 B4 BiDir D12 A5 A5 BiDir D13 B5 B5 BiDir D14 A6 A6 BiDir D15 B7 B7 BiDir REG00 H7 H7 Input REG01 H6 H6 Input RE...

Страница 23: ...D_ H3 H3 BiDir UNC_ G4 G4 BiDir R W_ H4 H4 Input DS G2 G2 Input The bi directional lines have internal pull ups of 45 KΩ These lines must be connected to additional external pull ups when connected across multiple chips ...

Страница 24: ...VDDC F4 F4 VDDC F5 F5 VDDC F7 F7 VDDC G5 G5 GND H8 H8 GND H1 H1 GND F6 F6 GND F3 F3 GND E5 E5 GND E4 E4 Power 3 3V Schematic Case VDDIO A7 A7 VDDIO B1 B1 VDDIO B8 B8 VDDIO C4 C4 VDDIO C8 C8 VDDIO D2 D2 VDDIO F8 F8 VDDIO G3 G3 VDDIO G7 G7 VDDIO G8 G8 VDDIO H2 H2 GND A1 A1 GND A8 A8 GND C3 C3 GND C6 C6 GND D4 D4 GND D5 D5 ...

Страница 25: ...ANICAL SPECIFICATIONS Die size 4 5 x 4 3 x 0 5 mm2 Process Geometry Technology 110 nm Packaging 64 pin CSP 4x4 mm Ball size 0 3 mm Ball pitch 0 5 mm NM500 is compliant to the JEDEC SOLID STATE TECHNOLOGY standard JESD22 102B ...

Страница 26: ...ature TOPR 40 25 125 Storage Temperature TSTG 55 150 8 2 DC ELECTRICAL CHARATERISTICS Parameters Symbol Value Unit Min Typ Max High level input voltage VIH 0 7 VDDIO 4 V Low level input voltage VIL 0 3 0 3 VDDIO V Switching threshold VT 1 31 1 41 1 54 V Schmitt trigger rising threshold VTP 1 6 1 69 1 78 V Schmitt trigger falling threshold VTN 1 18 1 27 1 36 V High level input current IIH 10 10 µA ...

Страница 27: ...ons per second The number of cycles for a recognition depends on the length L of the vector and the level of details expected in the recognition ranging from a simple status taking 1 Read command or the list of the K nearest neighbors with K ranging from 1 to a user defined value Operation Clock cycles 35 Mhz single chip L 256 N 576 K 3 18 Mhz multi chips L 256 N 576 K 3 Learn a vector of length L...

Страница 28: ...it take for the neurons to be ready after STDBY is de asserted o Next clock cycle How much power does the chip consume in standby o Should decrease by at least factor 10 according to specifications 10 2 FUNCTIONAL QUESTIONS The neurons do not learn nor recognize my vectors when I know it should Verify that the neurons are not in Save and Restore mode by reading the Network Status Register NSR If i...

Страница 29: ...M1K to the NM500 should be easy Combining the use of both types of chips in a same architecture is also possible provided that the slowest clock of the two is in effect Differences NM500 CM1K Nominal clock single chip 35 Mhz 27 Mhz Nominal clock multiple chip 18 Mhz 16 Mhz Optional Reco logic Registers 0x11 to 0x1F Output lines BUSY CAT_VAL DIST_VAL No Yes Optional I2C controller Output lines BUSY...

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