NEC VERSA 500D WINDOWS 98 - UPGRADE INFORMATION, Руководство по обслуживанию

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Troubleshooting and Repair 5-9
Table 5-4 BIOS Beep Codes
Beep
Code Diagnostic
Code
Description Test Performed
1-3-1 08h RAM refresh verification
test in progress or failure. Over a period of time, the refresh bit
(bit 4) in port 60h is read and tested.
The refresh bit should toggle from 0 to
1, then 1 to 0 within the time period.
Failure will result in system halt.
none 09h First 64K RAM test in
progress. No specific test is performed - just
indicates that the test is beginning .
1-3-3 0Ah First 64K RAM chip or
data line failure, multi-bit. The first 64K of RAM is tested with a
rolling ones test and a pattern test. If
any of the pattern tests fail, then the
BIOS reports that multiple data bits
failure. Failure results in a system halt.
1-4-2 0Dh Parity failure first 64K
RAM At the completion of the rolling ones
and pattern tests of the first 64K, the
BIOS checks the parity error bits (bits 7
and 6) of port 60h. Failure results in a
system halt.
2-1-1
2-1-2
2-1-3
2-1-4
2-2-1
2-2-2
2-2-3
2-2-4
2-3-1
2-3-2
2-3-3
2-3-4
2-4-1
2-4-2
2-4-3
2-4-4
10h-1Fh First 64K RAM chip or
data line failure on bit x The first 64K of RAM is tested with a
rolling ones test and a pattern test. If
any of the rolling ones tests fail, then
the BIOS reports the specific bit that
failed. To determine the bit number
from the diagnostic code, subtract 10h.
For example, if 12h is displayed at the
diagnostic port, bit 2 failed. Failure
results in a system halt.
3-3-1 20h Slave DMA register test in
progress or failure. Pattern test of channels 1 through 3 of
the slave controller (starting port
address = 02h). Failure results in a
system halt.