CHAPTER 14 INSTRUCTION SET
User's Manual U11919EJ3V0UM00
190
Flag
Mnemonic
Operands
Byte
Clock
Operation
Z
AC CY
A,#byte
2
4
A
−
byte
×
×
×
saddr,#byte
3
6
(saddr)
−
byte
×
×
×
A,r
2
4
A
−
r
×
×
×
A,saddr
2
4
A
−
(saddr)
×
×
×
A,!addr16
3
8
A
−
(addr16)
×
×
×
A,[HL]
1
6
A
−
(HL)
×
×
×
CMP
A,[HL+byte]
2
6
A
−
(HL+byte)
×
×
×
ADDW
AX,#word
3
6
AX,CY
←
AX + word
×
×
×
SUBW
AX,#word
3
6
AX,CY
←
AX
−
word
×
×
×
CMPW
AX,#word
3
6
AX
−
word
×
×
×
r
2
4
r
←
r + 1
×
×
INC
saddr
2
4
(saddr)
←
(saddr) + 1
×
×
r
2
4
r
←
r
−
1
×
×
DEC
saddr
2
4
(saddr)
←
(saddr)
−
1
×
×
INCW
rp
1
4
rp
←
rp + 1
DECW
rp
1
4
rp
←
rp
−
1
ROR
A,1
1
2
(CY,A
7
←
A
0
,A
m
−
1
←
A
m
)
×
1
×
ROL
A,1
1
2
(CY,A
0
←
A
7
,A
m+1
←
A
m
)
×
1
×
RORC
A,1
1
2
(CY
←
A
0
,A
7
←
CY,A
m
−
1
←
A
m
)
×
1
×
ROLC
A,1
1
2
(CY
←
A
7
,A
0
←
CY,A
m+1
←
A
m
)
×
1
×
saddr.bit
3
6
(saddr.bit)
←
1
sfr.bit
3
6
sfr.bit
←
1
A.bit
2
4
A.bit
←
1
PSW.bit
3
6
PSW.bit
←
1
×
×
×
SET1
[HL].bit
2
10
(HL).bit
←
1
saddr.bit
3
6
(saddr.bit)
←
0
sfr.bit
3
6
sfr.bit
←
0
A.bit
2
4
A.bit
←
0
PSW.bit
3
6
PSW.bit
←
0
×
×
×
CLR1
[HL].bit
2
10
(HL).bit
←
0
SET1
CY
1
2
CY
←
1
1
CLR1
CY
1
2
CY
←
0
0
NOT1
CY
1
2
CY
←
CY
×
Remark
One instruction clock cycle is one CPU clock cycle (f
CPU
) selected by processor clock control register
(PCC).
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