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CHAPTER 7 8-BIT TIMER/EVENT COUNTER

User's Manual U11919EJ3V0UM00

109

7.4 8-Bit Timer/Event Counter Operation

7.4.1 Operation as interval timer

Interval timer repeatedly generates an interrupt at time intervals specified by the count value set to 8-bit compare

To operate the 8-bit timer/event counter as an interval timer, the following settings are required.

<1> Disable the operation of 8-bit timer counter 00 (TM00) (TCE00 (bit 7 of 8-bit timer mode control register 00

(TMC00)) = 0).

<2> Set the count clock of the 8-bit timer/event counter (see Table 7-4).

<3> Set a count value in CR00.

<4> Enable the operation of TM00 (TCE00 = 1).

When the count value of the 8-bit timer counter 00 (TM00) coincides with the value set to CR00, the value of

TM00 is cleared to 0 and TM00 continues counting. At the same time, an interrupt request signal (INTTM0) is

generated.

Table 7-4 shows interval time, and Figure 7-4 shows the timing of interval timer operation.

Cautions 1. Before rewriting CR00, stop the timer operation. If CR00 is rewritten while the timer

operation is enabled, the coincidence interrupt request signal may be generated

immediately.

2. If setting the count clock in TMC00 and enabling the operation of TM00 are performed at the

same time with an 8-bit memory manipulation instruction, the error one cycle after the timer

has been started may exceed one clock. To use the 8-bit timer/event counter as an interval

timer, therefore, perform the setting in the above sequence.

Table 7-4. Interval Time of 8-Bit Timer/Event Counter 00

TCL001

TCL000

Minimum Interval Time

Maximum Interval Time

Resolution

1/f

(200 ns)

(51.2

1/f

(200 ns)

(6.4

(1.64 ms)

(6.4

TI0 input cycle

TI0 input edge cycle

TI0 input cycle

TI0 input edge cycle

Remarks 1. f

: System clock oscillation frequency

2. The parenthesized values apply to operation at f

= 5.0 MHz.

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Содержание UPD789026 Series

Страница 1: ...2 PD789024 PD789025 PD789026 PD78F9026A PD789026 Subseries 8 Bit Single Chip Microcontrollers 1998 Printed in Japan Document No U11919EJ3V0UMJ1 3rd edition Date Published October 2000 N CP K 1996 1999...

Страница 2: ...User s Manual U11919EJ3V0UM00 2 MEMO www DataSheet4U com...

Страница 3: ...TIMER 93 CHAPTER 7 8 BIT TIMER EVENT COUNTER 105 CHAPTER 8 WATCHDOG TIMER 115 CHAPTER 9 SERIAL INTERFACE 00 121 CHAPTER 10 INTERRUPT FUNCTIONS 149 CHAPTER 11 STANDBY FUNCTION 167 CHAPTER 12 RESET FUNC...

Страница 4: ...p or pull down circuitry Each unused pin should be connected to VDD or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must...

Страница 5: ...C semiconductor products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features NEC semiconductor products are classified i...

Страница 6: ...ins in Table 2 1 p 99 Addition of cautions on rewriting CR20 to Section 6 4 1 p 106 Addition of cautions on rewriting CR00 to Section 7 2 1 p 109 Addition of description of operation to Section 7 4 1...

Страница 7: ...many GmbH Duesseldorf Germany Tel 0211 65 03 02 Fax 0211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Italiana s r l Milano Italy Tel 02 66 75...

Страница 8: ...User s Manual U11919EJ3V0UM00 8 MEMO www DataSheet4U com...

Страница 9: ...set Instruction description How to Read This Manual It is assumed that the readers of this manual have general knowledge on electric engineering logic circuits and microcontrollers To understand the o...

Страница 10: ...U11599E U11599J RA78K0S Assembler Package Structured Assembly Language U11623E U11623J Operation U11816E U11816J CC78K0S C Compiler Language U11817E U11817J SM78K0S System Simulator Windows TM Based R...

Страница 11: ...531E C11531J NEC Semiconductor Device Reliability Quality Control System C10983E C10983J Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge ESD C11892E C11892J Semiconductor...

Страница 12: ...User s Manual U11919EJ3V0UM00 12 MEMO www DataSheet4U com...

Страница 13: ...Port 4 36 2 2 6 P50 to P53 Port 5 37 2 2 7 RESET 37 2 2 8 X1 X2 37 2 2 9 NC 37 2 2 10 VDD 37 2 2 11 VSS 37 2 2 12 VPP PD78F9026A only 37 2 2 13 IC mask ROM model only 38 2 3 Pin Input Output Circuits...

Страница 14: ...Functions 83 4 4 1 Writing to I O port 83 4 4 2 Reading from I O port 83 4 4 3 Arithmetic operation of I O port 83 CHAPTER 5 CLOCK GENERATION CIRCUIT 85 5 1 Function of Clock Generation Circuit 85 5 2...

Страница 15: ...Timer 119 8 4 1 Operation as watchdog timer 119 8 4 2 Operation as interval timer 120 CHAPTER 9 SERIAL INTERFACE 00 121 9 1 Serial Interface 00 Functions 121 9 2 Serial Interface 00 Configuration 121...

Страница 16: ...peration 185 14 1 1 Operand identifiers and writing methods 185 14 1 2 Description of Operation column 186 14 1 3 Description of Flag column 186 14 2 Operation List 187 14 3 Instructions Listed by Add...

Страница 17: ...ed to Stack Memory 55 3 15 Data to be Restored from Stack Memory 55 3 16 General Purpose Register Configuration 56 4 1 Port Types 69 4 2 Block Diagram of P00 to P07 71 4 3 Block Diagram of P10 to P17...

Страница 18: ...Timing with Rising Edge Specified 111 7 6 Square Wave Output Timing 113 7 7 8 Bit Timer Counter 00 Start Timing 114 7 8 External Event Counter Operation Timing 114 8 1 Block Diagram of Watchdog Timer...

Страница 19: ...on 163 10 14 Example of Nesting 164 11 1 Oscillation Settling Time Select Register Format 168 11 2 Releasing HALT Mode by Interrupt 170 11 3 Releasing HALT Mode by RESET Input 171 11 4 Releasing STOP...

Страница 20: ...Timer Event Counter 00 105 7 3 Configuration of 8 Bit Timer Event Counter 00 106 7 4 Interval Time of 8 Bit Timer Event Counter 00 109 7 5 Square Wave Output Range of 8 Bit Timer Event Counter 00 112...

Страница 21: ...ng Status 169 11 2 Operation after Release of HALT Mode 171 11 3 STOP Mode Operating Status 172 11 4 Operation after Release of STOP Mode 174 12 1 Hardware Status after Reset 177 13 1 Differences betw...

Страница 22: ...User s Manual U11919EJ3V0UM00 22 MEMO www DataSheet4U com...

Страница 23: ...cution time from high speed 0 4 s with 5 0 MHz system clock to slow 1 6 s with 5 0 MHz system clock I O port 34 lines Serial interface 1 channel 3 wire serial I O mode UART mode selection Timer 3 chan...

Страница 24: ...0 mil Mask ROM PD789025GB 3BS MTX 44 pin plastic QFP 10 10 mm resin thickness 2 7 mm Mask ROM PD789025GB 8ES 44 pin plastic LQFP 10 10 mm resin thickness 1 4 mm Mask ROM PD789026CU 42 pin plastic shri...

Страница 25: ...0 TI0 TO0 P32 INTP2 CPT2 P31 INTP1 P30 INTP0 P22 RxD SI0 P21 TxD SO0 P20 ASCK SCK0 P07 P06 P05 P04 P03 P02 P01 P00 VDD1 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VSS0 X1 X2 IC VPP...

Страница 26: ...3 4 5 6 7 8 9 10 11 P12 P11 P10 P47 KR7 P46 KR6 P45 KR5 P44 KR4 P43 KR3 P42 KR2 P41 KR1 P40 KR0 NC IC V PP X2 X1 V SS0 V DD1 RESET P53 P52 P51 TO2 P50 TI0 TO0 33 32 31 30 29 28 27 26 25 24 23 P03 P04...

Страница 27: ...NTP0 to INTP2 Interrupt from Peripherals SI0 Serial Input KR0 to KR7 Key Return SO0 Serial Output NC Non connection TI0 Timer Input P00 to P07 Port 0 TO0 TO2 Timer Output P10 to P17 Port 1 TxD Transmi...

Страница 28: ...pin PD789046 Device developed by adding the subsystem clock to the PD789026 30 pin 30 pin 30 pin 30 pin PD789124A PD789134A PD789217AY PD789197AY PD789177 PD789167 30 pin 30 pin PD789104A PD789114A Wi...

Страница 29: ...146 8 K to 16 K 4 ch EEPROM on chip PD789134A 4 ch PD789124A 4 ch RC oscillation PD789114A 4 ch General compact A D PD789104A 2 K to 8 K 1 ch 1 ch 1 ch 4 ch 1 ch UART 1 ch 20 1 8 V Inverter control PD...

Страница 30: ...NTERFACE 00 SI0 RxD P22 SCK0 ASCK P20 INTERRUPT CONTROL SYSTEM CONTROL INTP0 P30 to INTP2 CPT2 P32 KR0 P40 to KR7 P47 X1 X2 RESET PORT0 P00 to P07 PORT1 P10 to P17 PORT2 P20 to P22 PORT3 WATCHDOG TIME...

Страница 31: ...1 channel Timer output 2 Maskable Internal 5 External 4 Vectored interrupt source Non maskable Internal 1 Power supply voltage VDD 1 8 to 5 5 V Operating ambient temperature TA 40 C to 85 C Package 4...

Страница 32: ...User s Manual U11919EJ3V0UM00 32 MEMO www DataSheet4U com...

Страница 33: ...ed as input port on chip pull up resistor can be connected by setting of the pull up resistor option register PUO LEDs can be driven directly Input SI0 RxD P30 INTP0 P31 INTP1 P32 Input output Port 3...

Страница 34: ...P22 SI0 TxD Output Asynchronous serial interface serial data output Input P21 SO0 TO2 Output 16 bit timer TM20 output Input P51 CPT2 Input 16 bit timer capture edge input Input P32 INTP2 TI0 Input Ext...

Страница 35: ...output the data and clock of the serial interface This port can drive LEDs directly Port 2 can be specified in the following operation modes in bit wise 1 Port mode In this mode port 2 functions as a...

Страница 36: ...xternal interrupt input a INTP0 to INTP2 These pins input external interrupt for which effective edges rising edge falling edge and both the rising and falling edges can be specified b CPT2 This is a...

Страница 37: ...output a TI0 This is the external clock input pin for 8 bit timer event counter b TO0 This is an 8 bit timer output pin C TO2 This is a 16 bit timer output pin 2 2 7 RESET This pin inputs an active lo...

Страница 38: ...l operating mode directly connect the IC pin to the VSS0 or VSS1 pin with as short a wire as possible If a potential difference is generated between the IC pin and VSS0 or VSS1 pin due to a long wirin...

Страница 39: ...d Pins Pin Name I O Circuit Type Input Output Recommended Connection for Unused Pins P00 to P07 P10 to P17 5 X P20 ASCK SCK0 8 J P21 TxD SO0 5 X P22 RxD SI0 P30 INTP0 P31 INTP1 P32 INTP2 CPT2 P40 KR0...

Страница 40: ...ut Output Circuits Schmitt triggered input with hysteresis characteristics Type 2 IN VDD P ch IN OUT VDD0 P ch N ch Pullup enable Output data Output disable Type 8 J IN OUT VDD0 P ch VDD0 P ch N ch Pu...

Страница 41: ...e memory maps Figure 3 1 Memory Map PD789022 FFFFH FF00H FEFFH FE00H FDFFH 1000H 0FFFH 0000H 0FFFH 0000H 0080H 007FH 0040H 003FH 002CH 002BH Data Memory Space Program Memory Space Special Function Reg...

Страница 42: ...H FE00H FDFFH 2000H 1FFFH 0000H 1FFFH 0000H 0080H 007FH 0040H 003FH 002CH 002BH Data Memory Space Program Memory Space Special Function Registers 256 8 bits Internal High Speed RAM 256 8 bits Reserved...

Страница 43: ...FD00H FCFFH 3000H 2FFFH 0000H 2FFFH 0000H 0080H 007FH 0040H 003FH 002CH 002BH Data Memory Space Program Memory Space Special Function Registers 256 8 bits Internal High Speed RAM 512 8 bits Reserved...

Страница 44: ...FD00H FCFFH 4000H 3FFFH 0000H 3FFFH 0000H 0080H 007FH 0040H 003FH 002CH 002BH Data Memory Space Program Memory Space Special Function Registers 256 8 bits Internal High Speed RAM 512 8 bits Reserved...

Страница 45: ...00H FCFFH 4000H 3FFFH 0000H 3FFFH 0000H 0080H 007FH 0040H 003FH 002CH 002BH Data Memory Space Program Memory Space Special Function Registers 256 8 bits Internal High Speed RAM 512 8 bits Reserved Int...

Страница 46: ...ternal program memory space 1 Vector table area A 44 byte area of addresses 0000H to 002BH is reserved as a vector table area This area stores program start addresses to be used when branching by the...

Страница 47: ...pacity on each product The internal high speed RAM can also be used as a stack memory Table 3 3 Internal High Speed RAM Capacity Part Number Capacity PD789022 PD789024 256 8 bits PD789025 PD789026 PD7...

Страница 48: ...unctions of the special function registers SFR and other registers Figures 3 6 through 3 10 show the data memory addressing modes Notes 1 With PD789022 or PD789024 2 With PD789025 PD789026 or PD78F902...

Страница 49: ...FFH 2000H 1FFFH 0000H FF00H FEFFH FF20H FF1FH FE20H FE1FH Special Function Registers SFR 256 8 bits Internal High Speed RAM 256 8 bits Reserved Internal ROM 8 192 8 bits SFR Addressing Short Direct Ad...

Страница 50: ...FFH 3000H 2FFFH 0000H FF00H FEFFH FF20H FF1FH FE20H FE1FH Special Function Registers SFR 256 8 bits Internal High Speed RAM 512 8 bits Reserved Internal ROM 12 288 8 bits SFR Addressing Short Direct A...

Страница 51: ...FFH 4000H 3FFFH 0000H FF00H FEFFH FF20H FF1FH FE20H FE1FH Special Function Registers SFR 256 8 bits Internal High Speed RAM 512 8 bits Reserved Internal ROM 16 384 8 bits SFR Addressing Short Direct A...

Страница 52: ...4000H 3FFFH 0000H FD00H FCFFH FF00H FEFFH FF20H FF1FH FE20H FE1FH Special Function Registers SFR 256 8 bits Internal High Speed RAM 512 8 bits Reserved Internal Flash Memory 16 384 8 bits SFR Address...

Страница 53: ...the instruction to be fetched When a branch instruction is executed immediate data or register contents is set RESET input sets the reset vector table values at addresses 0000H and 0001H to the progra...

Страница 54: ...ag is reset to 0 upon DI instruction execution or interrupt acknowledgment and is set to 1 upon EI instruction execution b Zero flag Z When the operation result is zero this flag is set to 1 It is res...

Страница 55: ...fined be sure to initialize the SP before instruction execution Figure 3 14 Data to be Saved to Stack Memory Figure 3 15 Data to be Restored from Stack Memory 0 15 SP14 SP15 SP SP13 SP12 SP11 SP10 SP9...

Страница 56: ...sters in pairs can be used as a 16 bit register AX BC DE and HL They can be written in terms of functional names X A C B E D L H AX BC DE and HL and absolute names R0 to R7 and RP0 to RP3 Figure 3 16...

Страница 57: ...r This manipulation can also be specified with an address 16 bit manipulation Writes a symbol reserved with assembler for the 16 bit manipulation instruction operand When specifying an address write a...

Страница 58: ...ort mode register 1 PM1 FF22H Port mode register 2 PM2 FF23H Port mode register 3 PM3 FF24H Port mode register 4 PM4 FF25H Port mode register 5 PM5 FFH FF42H Timer clock select register 2 TCL2 R W 00H...

Страница 59: ...ister 0 IF0 FFE1H Interrupt request flag register 1 IF1 00H FFE4H Interrupt mask flag register 0 MK0 FFE5H Interrupt mask flag register 1 MK1 FFH FFECH External interrupt mode register 0 INTM0 FFF5H K...

Страница 60: ...ive addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the progr...

Страница 61: ...ransferred to the program counter PC and branched This function is carried out when the CALL addr16 or BR addr16 instruction is executed CALL addr16 and BR addr16 instructions can branch to all the me...

Страница 62: ...executed This instruction can refer to the address stored in the memory table 40H to 7FH and branch to all the memory spaces Illustration 15 1 15 0 PC 7 0 Low Addr High Addr Memory Table Effective Add...

Страница 63: ...ction execution 3 4 1 Direct addressing Function The memory indicated by immediate data in an instruction word is directly addressed Operand format Identifier Description addr16 Label or 16 bit immedi...

Страница 64: ...ter of the timer event counter are mapped and these SFRs can be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is set to 0...

Страница 65: ...essing is applied to the 240 byte spaces FF00H to FFCFH and FFE0H to FFFFH However the SFR mapped at FF00H to FF1FH can also be accessed with short direct addressing Operand format Identifier Descript...

Страница 66: ...xecuted When an 8 bit register is specified one of the eight registers is specified with 3 bits in the instruction code Operand format Identifier Description r X A C B E D L H rp AX BC DE HL r and rp...

Страница 67: ...ed is specified with the register pair specification code in the instruction code This addressing can be carried out for all the memory spaces Operand format Identifier Description DE HL Example MOV A...

Страница 68: ...Operand format Identifier Description HL byte Example MOV A HL 10H When setting byte to 10H Instruction Code 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 3 4 7 Stack addressing Function The stack area is indirectl...

Страница 69: ...wn in Figure 4 1 enabling various methods of control Alternate functions are provided in addition to the digital I O port function For more information on these alternate functions see Chapter 2 Figur...

Страница 70: ...input port on chip pull up resistor can be connected by setting of the pull up resistor option register PUO LEDs can be driven directly Input SI0 RxD P30 INTP0 P31 INTP1 P32 Input output Port 3 3 bit...

Страница 71: ...utput latch Port 0 can be specified in the input or output mode in 1 bit units by using the port mode register 0 PM0 When using P00 to P07 pins as input port pins on chip pull up resistors can be conn...

Страница 72: ...ns on chip pull up resistors can be connected in 8 bit units by using the pull up resistor option register PUO RESET input sets port 1 to input mode Figure 4 3 shows the block diagram of port 1 Figure...

Страница 73: ...ata I O and clock I O pins of the serial interface RESET input sets port 2 to input mode Figures 4 4 through 4 6 show the block diagrams of port 2 Caution When using the pins of port 2 as the serial i...

Страница 74: ...re 4 5 Block Diagram of P21 Internal Bus WRPUO RD WRPORT WRPM Output Latch P21 PM21 Selector PUO2 VDD0 P ch P21 TxD SO0 Alternate Function PUO Pull up resistor option register PM Port mode register RD...

Страница 75: ...re 4 6 Block Diagram of P22 Internal Bus WRPUO RD WRPORT WRPM Output Latch P22 PM22 Selector PUO2 VDD0 P ch P22 RxD SI0 Alternate Function PUO Pull up resistor option register PM Port mode register RD...

Страница 76: ...he pull up resistor option register PUO The pins of this port are also used as the external interrupt input and capture edge input RESET input sets port 3 to input mode Figure 4 7 shows the block diag...

Страница 77: ...he key return input RESET input sets port 4 to input mode Figure 4 8 shows the block diagram of port 4 Caution When using port 4 for the key return function it is necessary to set key return mode regi...

Страница 78: ...bit units by using the pull up resistor option register PUO The pins of this port are also used as the data I O pins of the timer RESET input sets port 5 to input mode Figures 4 9 through 4 11 show th...

Страница 79: ...ure 4 10 Block Diagram of P51 Internal Bus VDD0 P ch P51 TO2 WRPUO RD WRPORT WRPM PUO5 Output Latch P51 PM51 Alternate Function Selector PUO Pull up resistor option register PM Port mode register RD P...

Страница 80: ...igure 4 11 Block Diagram of P52 and P53 Internal Bus WRPUO RD WRPORT WRPM PUO5 Ouput Latch P52 P53 PM52 PM53 VDD0 P ch P52 P53 Selector PUO Pull up resistor option register PM Port mode register RD Po...

Страница 81: ...n the port function output mode is specified and the output level is changed the interrupt request flag is set When the output mode is used therefore the interrupt mask flag should be set to 1 beforeh...

Страница 82: ...mory manipulation instruction RESET input clears PUO to 00H Figure 4 13 Pull Up Resistor Option Register Format PMmn 0 Output mode output buffer ON Input mode output buffer OFF 1 Pmn Pin Input Output...

Страница 83: ...n that is set in the input mode and not subject to manipulation become undefined 4 4 2 Reading from I O port 1 In output mode The contents of an output latch can be read by using a transfer instructio...

Страница 84: ...User s Manual U11919EJ3V0UM00 84 MEMO www DataSheet4U com...

Страница 85: ...ing the STOP instruction 5 2 Configuration of Clock Generation Circuit The clock generation circuit consists of the following hardware Table 5 1 Configuration of Clock Generation Circuit Item Configur...

Страница 86: ...a 1 bit or 8 bit memory manipulation instruction RESET input sets PCC to 02H Figure 5 2 Processor Clock Control Register Format CPU Clock fCPU Selection PCC1 0 1 fX 0 2 s fX 22 0 8 s 0 0 0 0 0 0 PCC1...

Страница 87: ...or ceramic oscillation b External clock VSS0 VSS1 X1 X2 Crystal or Ceramic Resonator External Clock X1 X2 Caution When using the system clock oscillator circuit to avoid influence of wiring capacity e...

Страница 88: ...GENERATION CIRCUIT User s Manual U11919EJ3V0UM00 88 Figure 5 4 Incorrect Examples of Resonator Connection 1 2 a Too long wiring b Crossed signal line VSS0 VSS1 X1 X2 PORTn n 0 to 5 VSS0 VSS1 X1 X2 www...

Страница 89: ...d Current flowing through ground line of oscillation circuit potential at points A B and C fluctuates VSS0 VSS1 X1 X2 High Current VSS0 VSS1 X1 X2 Pmn VDD A B C High Current e Signal is extracted VSS...

Страница 90: ...C as follows a The slow mode 2 fCPU 1 6 s at 5 0 MHz operation of the system clock is selected when the RESET signal is generated PCC 02H While a low level is input to the RESET pin oscillation of the...

Страница 91: ...the CPU clock before switching 5 6 2 Switching CPU clock The following figure illustrates how the CPU clock switches Figure 5 5 Switching CPU Clock VDD RESET CPU Clock Slow Operation High Speed Opera...

Страница 92: ...User s Manual U11919EJ3V0UM00 92 MEMO www DataSheet4U com...

Страница 93: ...t Timer output Count value capture 1 Timer interrupt An interrupt is generated when a count value and compare value matches 2 Timer output Timer output control is possible when a count value and compa...

Страница 94: ...l register 16 bit timer mode control register 20 TMC20 Port mode register 5 PM5 Figure 6 1 Block Diagram of 16 Bit Timer 20 CPT2 P32 INTP2 Internal Bus Internal Bus 16 Bit Timer Mode Control Register...

Страница 95: ...nput clears this register to 0000H and after that to be in free running Cautions 1 The count value after releasing stop becomes undefined because the count operation is executed during the oscillation...

Страница 96: ...it timer 20 16 bit timer mode control register 20 TMC20 Port mode register 5 PM5 1 16 bit timer mode control register 20 TMC20 16 bit timer mode control register 20 TMC20 controls the setting of a cou...

Страница 97: ...TCL200 0 1 fX 22 1 25 MHz fX 26 78 1 kHz 16 bit Timer 20 Output Control Output disabled port mode Output enabled 16 bit Timer Counter 20 Count Clock Selection Overflow Flag Set Clear by reset and sof...

Страница 98: ...set the output latch of PM51 and P51 to 0 PM5 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM5 to FFH Figure 6 3 Port Mode Register 5 Format 1 1 1 1 PM53 PM52 PM51 PM5...

Страница 99: ...and CPT200 flags capture edge becomes setting prohibited When the count value of 16 bit timer counter 20 TM20 coincides with the value set to CR20 counting of TM20 continues and an interrupt request...

Страница 100: ...100 Figure 6 5 Timer Interrupt Operation Timing Count Clock TM20 Count Value CR20 INTTM2 TO20 TOF20 0000H 0001H N FFFFH 0000H 0001H N FFFFH N N N N N Interrupt Accepted Interrupt Accepted Overflow Fl...

Страница 101: ...TMC20 TO20 Output Enable Setting of Count Clock see Table 6 2 Inverse Enable of Timer Output Data Caution If both CPT201 flag and CPT200 flag are set to 0 the capture edge becomes operation prohibite...

Страница 102: ...tains the count value of 16 bit timer counter 20 TCP20 fetches count value within 2 clocks and retains the count value until the next capture edge detection Table 6 3 and Figure 6 9 show the setting c...

Страница 103: ...H and starts freerunning Figure 6 10 shows the timing of 16 bit timer counter 20 readout Cautions 1 The count value after releasing stop becomes undefined because the count operation is executed durin...

Страница 104: ...User s Manual U11919EJ3V0UM00 104 MEMO www DataSheet4U com...

Страница 105: ...ution 1 fX 200 ns 2 8 fX 51 2 s 1 fX 200 ns 2 5 fX 6 4 s 2 13 fX 1 64 ms 2 5 fX 6 4 s Remarks 1 fX System clock oscillation frequency 2 The parenthesized values apply to operation at fX 5 0 MHz 2 Exte...

Страница 106: ...Counter 00 TM00 2 Internal Bus TCE00 TCL001 TCL000 TOE00 8 Bit Timer Mode Control Register 1 F F P50 Output Latch PM50 Selector 1 8 bit compare register 00 CR00 This is an 8 bit register to compare th...

Страница 107: ...T input clears TMC00 to 00H Figure 7 2 8 Bit Timer Mode Control Register 00 Format TCE00 0 0 0 0 TCL001 TCL000 TOE00 TMC00 Symbol Address After Reset R W FF53H 00H R W 6 7 5 4 3 2 1 0 TCL001 0 0 1 1 8...

Страница 108: ...tput set PM50 and the output latch of P50 to 0 PM5 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM5 to FFH Figure 7 3 Port Mode Register 5 Format PM50 0 1 1 1 1 1 PM53...

Страница 109: ...4 shows interval time and Figure 7 4 shows the timing of interval timer operation Cautions 1 Before rewriting CR00 stop the timer operation If CR00 is rewritten while the timer operation is enabled t...

Страница 110: ...erval Timer Operation Timing Clear Clear Interrupt Accepted Interrupt Accepted Count Start Interval Time Interval Time Interval Time Count Clock TM00 Count Value CR00 TCE00 INTTM0 TO0 N 01 00 N 01 00...

Страница 111: ...0 coincides with the value set to CR00 the value of TM00 is cleared to 0 and TM00 continues counting At the same time an interrupt request signal INTTM0 is generated Figure 7 5 shows the timing of ext...

Страница 112: ...a match occurred the TM00 value will be cleared to 0 then resume to count generating an interrupt request signal INTTM0 Setting 0 to the bit 7 in TMC00 that is TCE00 makes the square wave output clea...

Страница 113: ...re 7 6 Square Wave Output Timing Clear Clear Interrupt Accepted Interrupt Accepted Count Start Count Clock TM00 Count Value CR00 TCE00 INTTM0 TO0Note N 01 00 N 01 00 N 00 01 N N N N Note The initial v...

Страница 114: ...TM00 started asynchronously with the count pulse Figure 7 7 8 Bit Timer Counter 00 Start Timing Count Pulse TM00 Count Value Timer starts 00H 01H 02H 03H 04H 2 Setting of 8 bit compare register 8 bit...

Страница 115: ...rtent loop is detected a non maskable interrupt or the RESET signal can be generated Table 8 1 Inadvertent Loop Detection Time of Watchdog Timer Inadvertent Loop Detection Time At fX 5 0 MHz 2 11 1 fX...

Страница 116: ...r clock select register 2 TCL2 Watchdog timer mode register WDTM Figure 8 1 Block Diagram of Watchdog Timer Internal Bus Internal Bus Prescaler Selector Control Circuit fX 26 fX 28 fX 210 3 7 Bit Coun...

Страница 117: ...ation instruction RESET input clears TCL2 to 00H Figure 8 2 Timer Clock Select Register 2 Format TCL22 0 0 1 1 0 0 0 0 0 TCL22 TCL21 TCL20 TCL2 R W R W 7 6 5 4 3 2 1 0 TCL21 0 1 0 1 fX 24 fX 26 fX 28...

Страница 118: ...ode 1 overflow and non maskable interrupt occur Watchdog timer mode 2 overflow occurs and reset operation started 0 0 Notes 1 Once RUN has been set to 1 it cannot be cleared to 0 by software Therefore...

Страница 119: ...to 1 the watchdog timer can be cleared and start counting If RUN is not set to 1 and the inadvertent loop detection time is exceeded the system is reset or a non maskable interrupt is generated by th...

Страница 120: ...d and a maskable interrupt INTWDT can be generated The priority of INTWDT is set as the highest of all the maskable interrupts The interval timer continues operation in the HALT mode but stops in the...

Страница 121: ...clock SCK0 and two for serial data SI0 SO0 The 3 wire serial I O mode supports simultaneous transmit and receive operation reducing data transfer processing time It is possible to switch the start bi...

Страница 122: ...ion Control Circuit Receive Shift Register RXS00 Receive Control Circuit Asynchronous Serial Interface Status Register 00 ASIS00 Direction Control Circuit Asynchronous Serial Interface Mode Register 0...

Страница 123: ...RXE00 f X ASCK SCK0 P20 1 2 1 2 CSIE00 RXE00 CSIE00 Internal Bus BRGC00 Write TXE00 CSCK00 RXE00 Transmit Clock Receive Clock Selector Clear Clear 3 Bit Counter Clear 3 Bit Counter Clear Stop Prescal...

Страница 124: ...register is used to hold received data Each time one byte of data is received a new byte of data is transferred from receive shift register 00 RXS00 If the data length is specified as 7 bits receive d...

Страница 125: ...interface 00 in the 3 wire serial I O mode CSIM00 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears CSIM00 to 00H Figure 9 3 Serial Operation Mode Register 00 Format CSI...

Страница 126: ...W FF70H 00H R W 7 6 5 4 3 2 1 0 Transmit operation stop Transmit operation enable Receive operation stop Receive operation enable RXE00 0 1 0 1 0 0 0 1 0 1 1 1 No parity Always add 0 parity at transmi...

Страница 127: ...ck SCK0 output 0 1 External clock SCK0 input 0 0 1 1 1 1Note 2 Note 2 0 1 0 1 LSB Internal clock SI0 Note 2 SO0 CMOS output SCK0 output Other than above Setting prohibited 3 Asynchronous serial interf...

Страница 128: ...0 Parity error not generated Parity error generated when the parity of transmit data does not coincide Flaming error not generated Flaming error generated when stop bit is not detected Note 1 Overrun...

Страница 129: ...1 0 n 1 2 3 4 5 6 7 8 Setting prohibited Symbol Address After Reset 3 Bit Counter Source Clock Selection Input clock from external to ASCK pinNote Other than above Note Only used in UART mode Caution...

Страница 130: ...rate generated from the system clock is found from the following expression Baud rate Hz fX System clock oscillation frequency n Value determined by values of TPS000 through TPS003 as shown in Figure...

Страница 131: ...baud rate generated from the clock input from the ASCK pin is found from the following expression Baud rate Hz fASCK Frequency of clock input to the ASCK pin Table 9 4 Relationship between ASCK Pin I...

Страница 132: ...TxD and P22 SI0 RxD pins can be used as normal I O ports 1 Register setting Operation stop mode is set by serial operation mode register 00 CSIM00 and asynchronous serial interface mode register 00 AS...

Страница 133: ...truction RESET input clears ASIM00 to 00H TXE00 0 1 Transmit Operation Control TXE00 RXE00 PS001 PS000 CL00 SL00 0 0 ASIM00 Symbol Address After Reset R W FF70H 00H R W 7 6 5 4 3 2 1 0 Transmit operat...

Страница 134: ...by serial operation mode register 00 CSIM00 asynchronous serial interface mode register 00 ASIM00 asynchronous serial interface status register 00 ASIS00 and baud rate generator control register 00 BR...

Страница 135: ...Transmit operation enable Receive operation stop Receive operation enable RXE00 0 1 0 1 0 0 0 1 0 1 1 1 No parity Always add 0 parity at transmission Parity check is not performed at reception No par...

Страница 136: ...nerated Framing error generated when stop bit is not detected Note 1 Overrun error not generated Overrun error generatedNote 2 when the next receive operation is completed before the data is read from...

Страница 137: ...rformed normally Be sure not to write to BRGC00 during communication operation 2 Be sure not to select n 1 during an operation at fX 5 0 MHz because n 1 exceeds the baud rate limit 3 When selecting an...

Страница 138: ...f baud rate transmit receive clock by means of external clock from ASCK pin The transmit receive clock is generated by scaling the clock input from the ASCK pin The baud rate generated from the clock...

Страница 139: ...1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit Start Bit One Data Frame Start bit 1 bit Character bits 7 bits 8 bits Parity bit Even parity odd parity 0 parity no parity Stop bit s 1 bit 2 bits When 7 bits a...

Страница 140: ...ed and if the number is odd a parity error is generated ii Odd parity At transmission Conversely to the even parity the parity bit is determined so that the number of bits with a value of 1 in the tra...

Страница 141: ...mission Completion Interrupt Timing a Stop bit length 1 STOP Parity D7 D6 D2 D1 D0 START TxD Output INTST b Stop bit length 2 STOP Parity D7 D6 D2 D1 D0 START TxD Output INTST Caution Do not rewrite t...

Страница 142: ...the start bit reception of one frame of data ends When one frame of data has been received the receive data in the shift register is transferred to receive buffer register 00 RXB00 and a reception co...

Страница 143: ...eive Error Causes Receive Error Cause Parity error Transmission time parity specification and reception data parity do not match Framing error Stop bit not detected Overrun error Reception of next dat...

Страница 144: ...6 RXE00 of asynchronous serial interface mode register 00 ASIM00 is cleared during reception receive buffer register 00 RXB00 and receive completion interrupt INTSR are as follows Parity RxD Pin RXB00...

Страница 145: ...mode register 00 CSIM00 asynchronous serial interface mode register 00 ASIM00 and baud rate generator control register 00 BRGC00 a Serial operation mode register 00 CSIM00 CSIM00 is set with a 1 bit...

Страница 146: ...5 4 3 2 1 0 Transmit operation stop Transmit operation enable Receive operation stop Receive operation enable RXE00 0 1 0 1 0 0 0 1 0 1 1 1 No parity Always add 0 parity at transmission Parity check...

Страница 147: ...munications cannot be performed normally Be sure not to write to BRGC00 during communication operation 2 Be sure not to select n 1 during an operation at fX 5 0 MHz because n 1 exceeds the baud rate l...

Страница 148: ...operations of TXS00 SIO00 and RXS00 stop automatically and the interrupt request signal INTCSI0 is generated Figure 9 11 3 Wire Serial I O Mode Timing 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 D...

Страница 149: ...he non maskable interrupt has one source of interrupt from the watchdog timer 2 Maskable interrupt These interrupts undergo mask control If two or more interrupts are simultaneously generated each int...

Страница 150: ...on External 000AH C INTSR End of serial interface 00 UART reception 4 INTCSI0 End of serial interface 00 3 wire transfer 000CH 5 INTST End of serial interface 00 UART transmission 000EH 6 INTTM0 Gener...

Страница 151: ...Internal maskable interrupt MK IF IE Internal Bus Interrupt Request Vector Table Address Generator Standby Release Signal C External maskable interrupt MK IF IE Internal Bus INTM0 KRM00 Interrupt Requ...

Страница 152: ...rogram status word PSW Key return mode register 00 KRM00 Table 10 2 gives a listing of interrupt request flag and interrupt mask flag names corresponding to interrupt requests Table 10 2 Flags Corresp...

Страница 153: ...s 1 to 6 of IF1 to 0 2 TMIF4 flag is R W enabled only when a watchdog timer is used as an interval timer If the watchdog timer mode 1 or 2 is used set TMIF4 flag to 0 3 Because port 3 has an alternate...

Страница 154: ...ter Reset Interrupt Servicing Control Interrupt servicing enabled Interrupt servicing disabled MK 6 5 4 3 2 1 7 0 TMMK20 1 1 1 1 1 1 KRMK00 MK1 FFE5H FFH R W 6 5 4 3 2 1 7 0 Cautions 1 Be sure to set...

Страница 155: ...s After Reset INTP0 Valid Edge Selection Falling edge Rising edge Setting prohibited Both rising and falling edges INTP1 Valid Edge Selection Falling edge Rising edge Setting prohibited Both rising an...

Страница 156: ...rry out operations with a bit manipulation instruction and dedicated instructions EI and DI When a vectored interrupt request is acknowledged PSW is automatically saved into a stack and the IE flag is...

Страница 157: ...KRM005 KRM004 0 0 0 KRM000 KRM00 Symbol Address After Reset R W FFF5H 00H R W 7 6 5 4 3 2 1 0 Cautions 1 Be sure to set bits 1 to 3 to 0 2 When KRM00 is set to 1 the corresponding pin is connected to...

Страница 158: ...ack in that order the IE flag is reset to 0 the contents of the vector table are loaded to the PC and then program execution branches Figure 10 8 shows the flowchart from non maskable interrupt reques...

Страница 159: ...DT overflows No Yes Reset Processing No Yes Yes Interrupt request is generated Interrupt processing is started WDTM3 0 non maskable interrupt is selected WDTM Watchdog timer mode register WDT Watchdog...

Страница 160: ...UNCTIONS User s Manual U11919EJ3V0UM00 160 Figure 10 10 Accepting Non Maskable Interrupt Request Second Interrupt Processing First Interrupt Processing NMI Request second NMI Request first Main Routin...

Страница 161: ...essing Minimum Time Maximum Time Note 9 clocks 19 clocks Note The wait time is maximum when an interrupt request is generated immediately before BT and BF instruction Remark 1 clock fCPU CPU clock Whe...

Страница 162: ...ram Algorithm Start IF 1 MK 0 IE 1 Vectored Interrupt Processing Yes Interrupt request generated Yes Yes No No No Interrupt Request Pending Interrupt Request Pending IF Interrupt request flag MK Inter...

Страница 163: ...ion Execution Saving PSW and PC jump to interrupt processing 8 Clocks Interrupt Processing Program Clock CPU Interrupt NOP MOV A r If an interrupt request flag IF is set at the last clock of the instr...

Страница 164: ...uest acceptance and the interrupt request acceptance enable state is set Example 2 A nesting is not generated because interrupts are not enabled INTyy EI Main Processing RETI INTyy Processing INTxx Pr...

Страница 165: ...next instruction even if the interrupt request maskable interrupt non maskable interrupt and external interrupt is generated during the execution The following shows such instructions interrupt reque...

Страница 166: ...User s Manual U11919EJ3V0UM00 166 MEMO www DataSheet4U com...

Страница 167: ...the entire system The current drain of the CPU can be substantially reduced in this mode Data memory can be retained at low voltages VDD 1 8 V min Therefore this mode is useful for retaining the conte...

Страница 168: ...tling Time Select Register Format OSTS2 0 0 1 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS R W FFFAH 04H R W 7 6 5 4 3 2 1 0 OSTS1 0 1 0 212 fX 215 fX 217 fX 819 s 6 55 ms 26 2 ms OSTS0 0 0 0 Setting prohibited S...

Страница 169: ...ing Status Item HALT Mode Operating Status Clock generation circuit System clock oscillation enabled Clock supply to CPU stopped CPU Operation stopped Port Output latch Retains the status before setti...

Страница 170: ...uted Figure 11 2 Releasing HALT Mode by Interrupt HALT Instruction Standby Release Signal Wait Wait HALT Mode Operation Mode Operation Mode Clock Oscillation Remarks 1 The broken line indicates the ca...

Страница 171: ...ms Reset Period HALT Mode Operation Mode Oscillation Settling Wait Status Clock Operation Mode Oscillation Stop Oscillation Oscillation Remarks 1 fX System clock oscillation frequency 2 The parenthesi...

Страница 172: ...by the oscillation settling time select register OSTS elapses and then operation mode is set The operation status in the STOP mode is shown in the following table Table 11 3 STOP Mode Operating Status...

Страница 173: ...upt processing is performed after the oscillation settling time has elapsed If the interrupt acceptance is disabled the instruction at the next address is executed Figure 11 4 Releasing STOP Mode by I...

Страница 174: ...6 55 ms STOP Mode Operation Mode Oscillation Settling Wait Status Clock Operation Mode Oscillation Stop Oscillation Oscillation Reset Period Remarks 1 fX System clock oscillation frequency 2 The pare...

Страница 175: ...uring oscillation settling time just after reset clear When a high level is input to the RESET pin the reset is cleared and program execution is started after the oscillation settling time 215 fX has...

Страница 176: ...ow in Watchdog Timer X1 Internal Reset Signal Port Pin Overflow in Watchdog Timer Normal Operation Reset Period oscillation continues Oscillation Settling Time Wait Normal Operation reset processing H...

Страница 177: ...ned Timer counter TM00 00H Compare register CR00 00H 8 bit timer event counter Mode control register TMC00 00H Timer clock select register TCL2 00H Watchdog timer Mode register WDTM 00H Mode register...

Страница 178: ...User s Manual U11919EJ3V0UM00 178 MEMO www DataSheet4U com...

Страница 179: ...ytes flash memory 4 Kbytes 8 Kbytes 12 Kbytes 16 Kbytes Internal memory Internal high speed RAM 512 bytes 256 bytes 512 bytes IC pin Not provided Provided VPP pin Provided Not provided Electric charac...

Страница 180: ...Table 13 2 To select a communication mode the format shown in Figure 13 1 is used Each communication mode is selected depending on the number of VPP pulses shown in Table 13 2 Table 13 2 Communication...

Страница 181: ...rased status of entire memory Data write Writes data to flash memory starting from write start address and based on number of data bytes to be written Batch verify Compares all contents of memory with...

Страница 182: ...026A VPPnNote VDD RESET SO SI GND VPP VDD0 VDD1 RESET RxD TxD VSS0 VSS1 Note n 1 2 Figure 13 4 Connection Example of Flashpro III in Pseudo 3 Wire Mode When using P0 VPPnNote VDD RESET SCK SO SI GND V...

Страница 183: ...MHz 0 COMM PORT UART ch0 CPU CLK On Target Board On Target Board 4 1943 MHz UART UART BPS 9 600 bps Note 2 8 COMM PORT Port A On Target Board CPU CLK In Flashpro On Target Board 4 1943 MHz SIO CLK 1 0...

Страница 184: ...User s Manual U11919EJ3V0UM00 184 MEMO www DataSheet4U com...

Страница 185: ...ecification Indirect address specification In the case of immediate data write an appropriate numeric value or a label When using a label be sure to write the and symbols For operand register identifi...

Страница 186: ...xiliary carry flag Z Zero flag IE Interrupt request enable flag NMIS Flag indicating non maskable interrupt servicing in progress Memory contents indicated by address or register contents in parenthes...

Страница 187: ...sfr A A addr16 3 8 A addr16 addr16 A 3 8 addr16 A PSW byte 3 6 PSW byte A PSW 2 4 A PSW PSW A 2 4 PSW A A DE 1 6 A DE DE A 1 6 DE A A HL 1 6 A HL HL A 1 6 HL A A HL byte 2 6 A HL byte MOV HL byte A 2...

Страница 188: ...6 A CY A HL ADD A HL byte 2 6 A CY A HL byte A byte 2 4 A CY A byte CY saddr byte 3 6 saddr CY saddr byte CY A r 2 4 A CY A r CY A saddr 2 4 A CY A saddr CY A addr16 3 8 A CY A addr16 CY A HL 1 6 A C...

Страница 189: ...r byte A r 2 4 A A r A saddr 2 4 A A saddr A addr16 3 8 A A addr16 A HL 1 6 A A HL AND A HL byte 2 6 A A HL byte A byte 2 4 A A byte saddr byte 3 6 saddr saddr byte A r 2 4 A A r A saddr 2 4 A A saddr...

Страница 190: ...4 saddr saddr 1 INCW rp 1 4 rp rp 1 DECW rp 1 4 rp rp 1 ROR A 1 1 2 CY A7 A0 Am 1 Am 1 ROL A 1 1 2 CY A0 A7 Am 1 Am 1 RORC A 1 1 2 CY A0 A7 CY Am 1 Am 1 ROLC A 1 1 2 CY A7 A0 CY Am 1 Am 1 saddr bit 3...

Страница 191: ...6 PC PC 2 jdisp8 if Z 1 BNZ saddr16 2 6 PC PC 2 jdisp8 if Z 0 saddr bit addr16 4 10 PC PC 4 jdisp8 if saddr bit 1 sfr bit addr16 4 10 PC PC 4 jdisp8 if sfr bit 1 A bit addr16 3 8 PC PC 3 jdisp8 if A...

Страница 192: ...1 None A ADD ADDC SUB SUBC AND OR XOR CMP MOVNote XCH Note ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH MOV XCH AD...

Страница 193: ...SP None AX ADDW SUBW CMPW MOVW XCHW MOVW MOVW rp MOVW MOVW Note INCW DECW PUSH POP saddrp MOVW SP MOVW Note Only when rp BC DE or HL 3 Bit manipulation instructions SET1 CLR1 NOT1 BT BF 2nd Operand 1...

Страница 194: ...ll instructions branch instructions CALL CALLT BR BC BNC BZ BNZ DBNZ 2nd Operand 1st Operand AX addr16 addr5 addr16 Basic instructions BR CALL BR CALLT BR BC BNC BZ BNZ Compound instructions DBNZ 5 Ot...

Страница 195: ...ompatibility with PC98 NX series Unless stated otherwise products which are supported for the IBM PC ATTM compatibles can also be used with the PC98 NX series When using the PC98 NX series therefore r...

Страница 196: ...package C compiler package System simulator Device file C compiler source file Integrated debugger Flash Memory Writing Environment In Circuit Emulator Emulation Probe Emulation board Flash writer Fl...

Страница 197: ...bler package CC78K0S C compiler package Part number S CC78K0S File containing the information inherent to the device Used in combination with other optional tools RA78K0S CC78K0S SM78K0S DF789026 Note...

Страница 198: ...B 8ES Flash memory writing adapter Flash memory writing adapter Used in connection with Flashpro III FA 42CU For 42 pin plastic shrink DIP CU type FA 44GB For 44 pin plastic QFP GB 3BS type FA 44GB 8E...

Страница 199: ...89026 NS EM1 Emulation board Emulation board for emulating the peripheral hardware inherent to the device Used in combination with in circuit emulator NP 44GB Note Emulation probe Emulation probe for...

Страница 200: ...stem to be used S ID78K0S NS Host Machine OS Supply Media AA13 PC 9800 series Japanese Windows Note 3 5 2HD FD AB13 IBM PC AT compatibles Japanese Windows Note 3 5 2HC FD Note Also operates under the...

Страница 201: ...44 B C M N O L K R Q I H P J G EV 9200G 44 G0 ITEM MILLIMETERS INCHES A B C D E F G H I J K L M O N P Q R 15 0 10 3 10 3 15 0 4 C 3 0 0 8 5 0 12 0 14 7 5 0 12 0 14 7 8 0 7 8 2 0 1 35 0 35 0 1 1 5 0 59...

Страница 202: ...57 0 03 0 618 0 433 0 433 0 618 0 197 0 197 0 02 0 062 0 087 0 062 0 8 0 02 10 8 0 0 05 0 8 0 02 10 8 0 0 05 0 002 0 001 0 002 0 002 0 002 0 001 0 002 0 002 0 003 0 004 0 003 0 004 0 001 0 002 0 001...

Страница 203: ...D H C 2 0 C 0 079 I 9 35 0 368 J 1 325 0 052 E 8 4 0 331 F 10 8 0 425 K 1 325 0 052 L 12 0 0 472 M Q 1 8 0 071 R S N 8 5 0 335 O 13 15 P 5 0 0 197 0 518 W X 6 0 0 236 Y T U 16 95 V 7 35 0 289 0 667 Z...

Страница 204: ...User s Manual U11919EJ3V0UM00 204 MEMO www DataSheet4U com...

Страница 205: ...OS controls task execution order and performs the switching process to a task to be executed Caution when used under the PC environment The MX78K0S is a DOS based application Use this software in the...

Страница 206: ...User s Manual U11919EJ3V0UM00 206 MEMO www DataSheet4U com...

Страница 207: ...146 Asynchronous serial interface status register 00 ASIS00 128 136 B Baud rate generator control register 00 BRGC00 129 137 147 E External interrupt mode register 0 INTM0 155 I Interrupt mask flag re...

Страница 208: ...Processor clock control register PCC 86 Pull up resistor option register PUO 82 R Receive buffer register 00 RXB00 124 Receive shift register 00 RXS00 124 S Serial operation mode register 00 CSIM00 12...

Страница 209: ...uest flag register 1 153 INTM0 External interrupt mode register 0 155 K KRM00 Key return mode register 00 157 M MK0 Interrupt mask flag register 0 154 MK1 Interrupt mask flag register 1 154 O OSTS Osc...

Страница 210: ...117 TCP20 16 bit capture register 20 95 TM00 8 bit timer counter 00 106 TM20 16 bit timer counter 20 95 TMC00 8 bit timer mode control register 00 107 TMC20 16 bit timer mode control register 20 96 T...

Страница 211: ...Chapter 9 Serial Interface 00 Change of flag names of interrupt request flag register Change of flag names of interrupt mask flag register Change of symbols and flag names of key return mode register...

Страница 212: ...User s Manual U11919EJ3V0UM00 212 MEMO www DataSheet4U com...

Страница 213: ...51 Address North America NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Technical Documentation Dept Fax 49 211 6503 274 South A...

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