NEC uPD75P308 Скачать руководство пользователя страница 32 | Manualshive

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PD75P308

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APPENDIX B. RELATED DOCUMENTS

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Содержание uPD75P308

Страница 1: ...er s Manual IEM 5016 The function common to the one time PROM and EPROM types of product is referred to as PROM throughout this document The information in this document is subject to change without n...

Страница 2: ...S4 S3 S2 S1 S0 RESET P73 KR7 P72 KR6 P71 KR5 P70 KR4 P63 KR3 P62 KR2 P61 KR1 P60 KR0 X2 X1 V XT2 XT1 V P33 MD3 P32 MD2 P31 SYNC MD1 P30 LCDCL MD0 P23 BUS P22 PCL P21 P20 PTO0 P13 TI0 P12 INT2 P11 INT1...

Страница 3: ...MEMORY RAM 512 x 4 BITS CY ALU VSS VDD VPP DECODE AND CONTROL PROGRAM MEMORY PROM 8064 x 8 BITS PROGRAM COUNTER 13 STAND BY CONTROL SYSTEM CLOCK GENERATOR CLOCK DIVIDER CLOCK OUTPUT CONTROL SUB MAIN f...

Страница 4: ...AND PD75308 10 3 WRITING AND VERIFYING PROM PROGRAM MEMORY 11 3 1 OPERATION MODES FOR WRITING VERIFYING PROGRAM MEMORY 11 3 2 PROGRAM MEMORY WRITE PROCEDURE 12 3 3 PROGRAM MEMORY READ PROCEDURE 13 3...

Страница 5: ...ftware Input Input 1 bit output port BIT PORT Shared with a segment output pin G C 3 X F A F A Input Output Input Output Output Output Input Output Input Output With noise elimination function 4 bit i...

Страница 6: ...s a 1 bit input test pin System reset input low level active To select mode when writing verifying of program memory PROM Program voltage application when writing and verifying of program memory PROM...

Страница 7: ...ch Push pull output that can be set in a output high impedance state both P ch and N ch are off IN Schmitt trigger input with hysteresis characteristics data output disable Type D Type A P U R enable...

Страница 8: ...C0 VLC1 VLC2 P ch N ch SEG data COM data OUT P ch N ch N ch P ch data output disable Type D Type B P U R enable VDD P ch IN OUT P U R Pull Up Resistor TYPE F B P U R Pull Up Resistor data output disab...

Страница 9: ...t This means that even during ordinary operation the PD75P308 may be set in the test mode if a noise exceeding VDD is applied For example if the wiring length of the P00 INT4 or RESET pin is too long...

Страница 10: ...of a mask ROM Programs can be rewritten to the PROM of the PD75P308 Table 2 1 shows the differences between the PD75P308 and PD75308 You should fully consider these differences when you debug or prod...

Страница 11: ...ted by the clock input through the X1 pin These pins input output 8 bit data when program memory is written verified VDD X1 X2 Note 1 Always cover the erasure window of the PD75P308K with a light opaq...

Страница 12: ...as been written connectly proceed to step 10 If data has not yet been written repeat steps 7 to 9 10 Write additional data for the number of times data was written X in steps 7 to 9 times 1 millisecon...

Страница 13: ...ear mode 5 Supply 6 V to the VDD pin and 12 5 V to the VPP pin 6 Set program inhibit mode 7 Set verify mode Data of each address is sequentially output each time a clock pulse is input to the X1 pin f...

Страница 14: ...y 12 mW cm2 is used about 15 to 20 minutes is required Note 1 The contents of the program memory may be erased when the PD75P308 is exposed for a long time to direct sunlight or the light of fluoresce...

Страница 15: ...5 mA IOH All pins 30 mA Peak value 30 mA Effective value 15 mA Peak value 100 mA Effective value 60 mA Peak value 100 mA Effective value 60 mA Operating Temperature Topt 10 to 70 C Storage Temperature...

Страница 16: ...n frequency is 4 19 MHz fx 5 0 MHz do not select PCC 0011 as the instruction execution time otherwise one machine cycle is set to less than 0 95 s falling short of the rated minimum value of 0 95 s Ca...

Страница 17: ...oss the wiring over the other signal lines Do not route the wiring in the vicinity of lines through which a high alternating current flows Always keep the ground point of the capacitor of the oscillat...

Страница 18: ...Output Voltage Deviation Segment Supply Current 0 7 VDD VDD V 0 8 VDD VDD V 0 7 VDD 10 V VDD 0 5 VDD V 0 0 3 VDD V 0 0 2 VDD V 0 0 4 V VDD 1 0 VDD 2 0 V 0 4 V 1 0 V 3 A 20 A 20 A 3 A 20 A 3 A 20 A 3 A...

Страница 19: ...nputHigh Low Level Widths RESET Low Level Width 0 95 64 s 114 122 125 s 0 1 MHz 0 48 s 2 s 10 s 10 s 0 1 2 3 4 5 6 0 5 1 2 3 4 5 6 60 64 70 with main system clock Cycle time t s cy Supply voltage V V...

Страница 20: ...vs SCK SI Hold Time vs SCK SCK SO Output Delay Time RL and CL are load resistance and load capacitance of the SO output line TWO LINE AND THREE LINE SERIAL I O MODES SCK external clock input RL and CL...

Страница 21: ...KSB tSBK tSBL tSBH RL and CL are load resistance and load capacitance of the SO output line SBI MODE SCK external clock output master RL and CL are load resistance and load capacitance of the SO outpu...

Страница 22: ...C TIMING TEST POINT excluding X1 and XT1 inputs Test points 0 8 VDD 0 2 VDD 0 8 VDD 0 2 VDD CLOCK TIMING X1 input VDD 0 5V 0 4 V tXL tXH 1 fX XT1 input VDD 0 5V 0 4 V tXTL tXTH 1 fXT TI0 tTIL tTIH 1 f...

Страница 23: ...PD75P308 23 SERIAL TRANSFER TIMING THREE LINE SERIAL I O MODE SCK tKL1 tKH1 tKCY1 Output data tSIK1 tKSI1 tKSO1 Input data SI SO TWO LINE SERIAL I O MODE SCK tKL tKH tKCY tSIK tKSI SB0 1 tKSO...

Страница 24: ...RANSFER RESET INPUT TIMING INT0 1 2 4 KR0 7 tINTL tINTH INTERRUPT INPUT TIMING SCK tKL3 4 tKCY3 4 tSIK3 4 tKSI3 4 tKSO3 4 SB0 1 tKH3 4 tSBK tKSB COMMAND SIGNAL TRANSFER RESET tRSL SCK tKL3 4 tKCY3 4 t...

Страница 25: ...le operation when oscillation is started 3 Depends on the setting of the basic interval timer mode register BTM as follows BTM3 BTM2 BTM1 BTM0 WAIT time fX 4 19 MHz 0 0 220 fX approx 250 ms 0 1 217 fX...

Страница 26: ...ime vs MD3 VDD Set Up Time vs MD3 Initial Program Pulse Width Additional Program Pulse Width MD0 Set Up Time vs MD1 MD0 Data Output Delay Time MD1 Hold Time vs MD0 MD1 Recovery Time vs MD0 Program Cou...

Страница 27: ...S t tDS tDH t tDV tDF tDS tAH tAS tOPW t tM1R tPW tPCR tM1S tM1H tM3S tM3H tVPS tVDS t tDV tXH tXL tHAD tDAD Data output Data output tDFR tM3HR tPCR tM3SR tXH tXL I OH MOS I X1 P40 P43 P50 P53 VPP VDD...

Страница 28: ...35 0 10 0 15 20 0 0 2 0 929 0 016 0 039 0 031 0 006 0 031 T P 0 795 NOTE M N 0 15 0 15 1 8 0 2 0 8 T P 0 006 0 006 0 004 0 003 Each lead centerline is located within 0 15 mm 0 006 inch of its true po...

Страница 29: ...B C D E F G H I J K Q R S T U W 20 0 0 4 19 0 13 2 14 2 0 4 1 64 2 14 4 064 MAX 0 51 0 10 0 08 0 8 T P 1 0 0 2 C 0 5 0 8 1 1 R 3 0 12 0 0 75 0 2 0 787 0 748 0 520 0 559 0 016 0 065 0 084 0 160 MAX 0...

Страница 30: ...s of pre baking is required at 125 C Infrared Reflow Package peak temperature 230 C IR30 162 1 time 30 seconds max 210 C min number of times 1 maximum number of days 2 days beyond this period 16 hours...

Страница 31: ...08K It is connected to PG 1500 Software IE Control Program Host machine PG 1500 Controller PC 9800 series MS DOSTM Ver 3 30 to Ver 5 00A 3 RA75X Relocatable IBM PC ATTM PC DOSTM Ver 3 1 Assembler APPE...

Страница 32: ...PD75P308 32 APPENDIX B RELATED DOCUMENTS...

Страница 33: ...generated due to noise and an inrush current may flow through the device causing the device to malfunction Therefore fix the input level of the device by using a pull down or pull up resistor If there...

Страница 34: ...ration or others The devices listed in this document are not suitable for uses in aerospace equipment submarine cables nuclear reactor control systems and life support systems If customers intend to u...

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