NEC N8, Руководство по обслуживанию

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NEC Confidential & Proprietary
4. TRANSMITTER
The IC121 generates a modulated signal at IF with a quadrature modulator and converts
it to final frequency with an Offset Phase Locked Loop (OPLL).
The Offset Phase Locked Loop is simply a PL L with a down conversion mixer in the
feedback path. Using a down converter in the feedback path acts as an up-converter in
the forward path. This allows the output frequency to be different from the comparison
frequency without affecting the normal operation of the loop. Phase/frequency changes
in the reference signal are not scaled, as they would be if a divider were used in the
feedback path, hence the modulation is faithfully reproduced at the final frequency.
The main advantage of the OPL L in this application is that it forms a tracking band pass
filter around the modulated signal. This is because the loop cannot respond to phase
variations at the reference that are outside its closed loop bandwidth. Thus the broad
band phase noise from the quadrature modulator is shaped by the frequency response
of the closed loop allowing the T X noise specification to be met without further filtering.
A secondary advantage of the OPLL is that the output signal, coming from a VCO, is truly
constant envelope. This removes the problem of spectral spreading caused by AM to AM
and AM to PM conversion in the power amplifier. The OPLL is formed from an on chip
Gilbert cell down converter, limiter and phase detector with off chip passive loop filter
and VCO. The phase detector is implemented as a Gilvert cell with current source output
stage. The current output allows an integrator to be included in the passive loop filter.
This is similar to the technique commonly used in PL L synthesizers. The closed loop
bandwidth of the OPL L should be designed to be around 1.0 ~ 1.5MHz. The bandwidth
should be large enough to allow rapid locking and accurate tracking of the modulation. If
the bandwidth is too large, the OPLL will not reject the noise from the modulator
sufficiently. The ideal bandwidth will be a compromise between these factors depending
on the noise performance of the VCO and amplifier chain. Moreover, the OPLL phase
detector current automatically changes between GSM900, DCS1800 and PCS1900
typically in the ratio 2:1:1 This can afford to use the same values for the external passive
components of loop filter in each band (GSM900, DCS1800 and PCS1900) without any
change.
IC121 includes two frequency synthesizers. The synthesizers control the RF VCO which
sets the operating channel and the fixed IF VCO. Charge-pump phase comparators are
used. The phase detector currents are programmable. The RF synthesizer has a
programmable fastlock system to reduce the acquisition time. During fastlock the phase
detector output current is increased from the normal current to the fastlock current, and
a MOS transistor connects a second resistor into the loop filter. At the end of the fastlock
period, the phase detector current reverts to the normal value and the MOS switch
opens. The fastlock period is set by a 6 bit number in the RF synthesizer reference word.
Moreover, the transition from fastlock to normal operation should occur synchronously
with the charge pump output to minimize the disturbance to the loop.
The synthesizers are programmed with 24 bit or 20 bit control words. The output current
of the phase detector is also programmed through the RF synthesizer control registers.
Therefore, the same VCO and loop filter can be used on each bands.