NEC MultiSync FP1355 FP1355 FP1355, Руководство по обслуживанию

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The vertical system DBF compensation waveform is output from pin58 in the 1-bit DAC mode.
Pin 58 direct outputs the pulse waveform of the resolution power of 25MHz. The pulse wave-
form is smoothened with the low pass filter of R621 and C607 to gain the DBF compensation
waveform of the vertical frequency. The amplitude is approximately 0.6Vp-p. It is connected
to pin 3 of IC6A2.
1.8.6 Convergence compensation waveform generating circuit
The horizontal dynamic convergence compensation waveform is output from pin 6 of IC601 in
the 8-bit DAC mode. The amplitude is approximately 0V to 0.5V. The vertical dynamic conver-
gence compensation waveform is output from pin 8 in the 10-bit DAC mode. The amplitude is
approximately 0V to 0.5V. The dynamic convergence compensation waveform center voltage
(approx. 1.6V) is output from pin 7.
In the 1-bit DAC mode, the horizontal static convergence compensation waveform is output
from pin 61, and the vertical static convergence compensation waveform is output from pin 60.
In pins 60 and 61 direct, the pulse waveform of the resolution power of 25MHz is output. The
pulse waveform is smoothened through the low pass filter to gain the horizontal static conver-
gence compensation waveform and vertical static convergence compensation waveform of the
vertical frequency.
1.8.7 Blanking waveform generating circuit
The horizontal blanking pulse and vertical blanking pulse are generated in IC601, and these
two waveforms are mixed and output at 3.3Vp-p from pin 40 of IC601.
The reference of the phase of the vertical blanking pulse is determined at the leading edge of
VFLY (vertical flyback pulse, 5V pulse) of pin 39 input of IC601, and the phase can be variably
controlled to output the optimal waveform of the blanking pulse.
The horizontal blanking pulse is a pulse that is synchronized with H-IN (horizontal sync. signal,
5V pulse) of pin 44 input of IC601, and can be also variably controlled.
The waveform is connected to pin 6 of the preamplifier (IC211) of the video board.
1.8.8 Moire canceling circuit
The moire canceling circuit outputs the waveform that is reversed every line of the horizontal
frequency and every 1 frame of the vertical frequency from pin 22. The vertical frequency
waveform is output from pin 23, and these two waveforms are added to the horizontal PLL
through the filter of R630 and C618 to achieve the moire canceling function.
Pin 30 of IC601 is a terminal to detect the drop of the power voltage (+3.3V), and the detection
voltage is approximately 1.0V. When a power voltage drop is detected, pin 32 of IC601 varies
from Hi level (5V) to Lo level (0V) but is not used now.
Pin 46 is a terminal to detect whether the horizontal PLL is locked and HD output from pin 25 is
normal or not. It is output at the Hi level (5V) when it is locked, and at the Lo level (0V) when it
is unlocked. It is connected to IC103 (MPU).
Pin 49 is the reset terminal of IC601. The reset IC of IC6A4 resets IC601 when P-OFF+5V
drops to approx. 2.7V.