NEC MultiSync FP1355 FP1355 FP1355, Руководство по обслуживанию

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1.8.3 Horizontal deflection drive waveform generating circuit
The rectangular wave for horizontal deflection drive are output at the amplitude 3.3Vp-p and
approx. 45% Duty from IC601 pin 25 with the delay of the transistor taken into account in order
to make the Duty become 50% at the output of Q501 of the horizontal deflection circuit.
Here, the simulative horizontal sync. signal (5V pulse) from the horizontal flyback pulse (AFC,
5V pulse) input to IC601 pin 27 and IC101 (MPU) input to IC601 pin 44 is passed through the
invertor of IC6A1 to produce the edges of these waveforms. This prevents the noises of the
jitter , etc. from generating.
Moreover, the circuit composed of Q602, Q605 , etc. connected to IC601 pin 13 prevents the
rapid frequency variation of the horizontal output when the horizontal input signal becomes no
signal. IC601 pin 13 is a phase comparator filter terminal to phase-lock the horizontal input
sync. signal and the oscillation in IC601. When the horizontal input sync. signal becomes no
signal, the terminal voltage rapidly varies from approx. 0.8V of the phase lock time to 0V, and
the frequency of the horizontal output rapidly varies according to this. The circuit is added to
compress the rapid frequency variation width by smoothening the variation of the terminal
voltage of pin 13 by C636 when it becomes unlocked. This prevents the horizontal collector
pulse from jumping in order to prevent overvoltage against the horizontal output transistor
(Q502).
The terminals pin 13 to pin 20 of IC601 become the control filter terminal of horizontal PLL.
1.8.4 Distortion compensation waveform generating circuit
The deflection distortion compensating waveform is output from pin 64 of IC601. The waveform
is output from 1-bit DAC, and 3.3V pulse waveform of resolution power of 25MHz is output at
pin64 direct. The pulse waveform is smoothened with the low pass filter of R632 and C622 to
gain the compensation waveform of the vertical frequency. The amplitude is approximately 1.0
to 1.2Vp-p, and is connected to pin5 of IC5J1.
The horizontal size, trapezoid compensation, side pin compensation, upper/lower compensation
of the side pin, S type compensation of the side pin and W compensation of the side pin are
applied. (Refer to the compensation image, figure 22.)
The deflection compensation waveform in the horizontal phase system is output from pin 57 of
IC601. Pin 57 is the 1-bit DAC output, and outputs the pulse waveform of 3.3V of resolution
power of 25MHz. The pulse waveform is smoothened with the low pass filter of R614, R619,
C601 and C604, and the waveform of the vertical frequency is current-added to the filter (pin
20 of IC700) of the horizontal system PLL to compensate for the deflection distortion of the
horizontal phase system. The parallel rectangular distortion compensation and the side pin
balance (upper and lower) compensation are executed. (Refer to the compensation image,
figure 22.)
1.8.5 DBF compensation waveform generating circuit
The horizontal system DBF compensation waveform is output in 8-bit DAC mode from pin 10 of
IC601. The amplitude is approximately 0.5Vp-p. It is connected to pin 6 of IC6A2.
50
`
77.9Hz
78
`
89.9Hz
90
`
124.9Hz
125
`
160Hz
Vertical frequency
OFF
ON
OFF
ON
Q604 Q603
OFF
OFF
ON
ON
Table 12 Vertical linearity compensation resistance select transistor ON/OFF