49
µ
PD754202, 754202(A)
0.5
0
1
2
3
4
5
6
1
2
3
4
5
6
60
64
Supply voltage V
DD
[V]
(During system clock operation)
t
CY
vs V
DD
Operation
guaranteed range
Cycle time t
CY
[ s]
µ
AC Characteristics (T
A
= –40 to +85
°
C, V
DD
= 1.8 to 6.0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
CPU clock cycle time
Note 1
t
CY
When system
2.7 V
≤
V
DD
≤
6.0 V
0.67
64.0
µ
s
(Minimum instruction execution
clock is used
time = 1 machine cycle)
1.8 V
≤
V
DD
< 2.7 V
0.95
64.0
µ
s
Interrupt input high- and
t
INTH
, t
INTL
INT0
IM02 = 0
Note 2
µ
s
low-level widths
IM02 = 1
10
µ
s
KR4-KR7
10
µ
s
RESET low-level width
t
RSL
10
µ
s
Notes 1.
The CPU clock (
Φ
) cycle time (minimum
instruction execution time) is determined
by the oscillation frequency of the con-
nected resonator (and external clock) and
the processor clock control register (PCC).
The figure on the right shows the cycle
time t
CY
characteristics against the supply
voltage V
DD
when the system clock is used.
2.
2t
CY
or 128/fx depending on the setting of
the interrupt mode register (IM0).
Содержание Mu754202
Страница 63: ...63 µPD754202 754202 A MEMO ...
