NEC mPD789101, Руководство пользователя

Страница: 92 / 265

User’s Manual U13045EJ2V0UM00
92
CHAPTER 6 CLOCK GENERATOR (
µ
PD789104, 789114 SUBSERIES)
6.4.2 Divider
The divider divides the output of the system clock oscillator (f
X
) to generate various clocks.
6.5 Operation of Clock Generator
The clock generator generates the following clocks and controls the operating modes of the CPU, such as the
standby mode:
• System clock f
X
• CPU clock f
CPU
• Clock to peripheral hardware
The operation of the clock generator is determined by the processor clock control register (PCC), as follows:
(a) The slow mode 2f
CPU
(1.6
µ
s: at 5.0-MHz operation) of the system clock is selected when the RESET signal
is generated (PCC = 02H). While a low level is input to the RESET pin, oscillation of the system clock is
stopped.
(b) Two types of CPU clocks f
CPU
(0.2
µ
s and 0.8
µ
s: at 5.0-MHz operation) can be selected by the PCC setting.
(c) Two standby modes, STOP and HALT, can be used.
(d) The clock to the peripheral hardware is supplied by dividing the system clock. The other peripheral
hardware is stopped when the system clock is stopped (except the external clock input operation).