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CHAPTER 14 SERIAL INTERFACE SIO2
Preliminary User’s Manual U14581EJ3V0UM00
Figure 14-8 shows the status of each register (SIO2, SIRB2, SRBS2) during a receive operation.
Figure 14-8. Receive Operation
SIO2
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA1
DATA2
DATA5
DATA6
DATA2
DATA1
DATA3
DATA4
DATA5
DATA6
SIRB2
SDVA
SDOF
SIRB2 read
Data reception end
SRBS2 read
INTCSI2
(4)
(10)
(11)
(3)
(9)
(2)
(1)
(5)
(6)
(8)
(7)
(1)
After DATA1 (receive data) is received completely, it is transferred to SIRB2.
(2)
SDVA is set since the receive data is transferred to SIRB2.
(3)
SDVA is automatically cleared to 0 by SIRB2 read.
(4)
SRBS2 is read and the status is checked (overflow error check).
(5)
Like (1) above, DATA2 (receive data) is transferred to SIRB2 after it is received completely.
(6)
Even though DATA3 (receive data) reception is complete, it is held in SIO2 without being transferred to SIRB2
since the previous receive data (DATA2) has not been read from SIRB2.
(7)
SDOF is set to 1 since SDVA has been set to 1 and DATA3 reception for SIO2 is complete.
(8)
DATA3 (receive data) is discarded and DATA4 (receive data) reception ends.
Like (6) above, DATA4 is not transferred to SIRB2 and is held in SIO2.
(9)
Like (3) above, SDVA is automatically cleared to 0 by SIRB2 read.
(10)
SDOF is automatically cleared to 0 by SRBS2 read.
(11)
Like (1) above, after DATA5 (receive data) is received completely, DATA5 is transferred to SIRB2.
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