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Chapter 9
Clock Generator
Preliminary User’s Manual U15839EE1V0UM00
9.4.5 IDLE
Mode
In this mode, the CPU clock is stopped resulting in stop of the entire system, though the clock genera-
tors (oscillator, SSCG and PLL synthesizer) continue to operate.
As it is not necessary to secure the oscillator oscillation stabilization time and the PLL lock-up time, it is
possible to quickly switch to the normal operating mode in response to a release cause. The IDLE
mode can be entered by configuration the PSM and PSC registers.
In the IDLE mode, program execution is stopped but the contents of all registers and internal RAM prior
to entering this mode are retained. On-chip peripheral hardware operation is also stopped.
The state of the various hardware units in the IDLE mode is tabulated below.
Table 9-6:
Operating States in IDLE Mode
IDLE mode release:
Release operation is same as release from HALT mode.
The IDLE mode is released by NMI, RESET signal input, or an unmasked maskable interrupt
request.
(a) Release by Interrupt input:
When the IDLE mode is released, the NMI request is acknowledged.
If the IDLE mode is entered during the execution of NMI handler, the IDLE mode is released but
the interrupt is not acknowledged. The interrupt itself is retained.
(b) Release by RESET input:
This operation is the same as normal reset operation.
Items
Operation
Clock generator
Operating
SSCG/PLL
Operating
Internal system clock
Stopped
WT, WDT clock
Operating
CPU
Stopped
I/O line
Unchanged
Peripheral function
Stops exclude Watch timer / Watchdog timer
TMC calibration input
Main Clock available
Internal data
Retains all internal data before entering IDLE mode, such
as CPU registers, status, data, and on-chip RAM.
D[15:0], A[23:0]
Hi-Z
RD, WR1/WR0, CS[0], CS[4:2]
H
CLKOUT
L
WAIT
Input value is not sampled
Содержание mPD703128
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