NEC IE-784225-NS-EM1, Руководство пользователя

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CHAPTER 4 DIFFERENCES BETWEEN TARGET DEVICES AND TARGET INTERFACE CIRCUITS
User’s Manual U13742EJ2V0UM
38
(2) Signals input from the target system via a gate
Since the following signals are input via a gate, their timing shows a delay compared to that of the
µ
PD784225
Subseries. Their AC characteristics and DC characteristics are therefore different from
µ
PD784225 Subseries,
making it necessary to observe a stricter timing design than in the case of
µ
PD784216A, 784216AY, 784218A,
784218AY, and 784225 Subseries.
•
RESET signal
•
Signals related to clock input
Figure 4-3. Equivalent Circuit 3 of Emulation Circuit
LV
CC
4.7 k
Ω
V
CC
4.7 k
Ω
24
Ω
ALTERA
EPM7128-15
HD151015
HD151015
VHC244
RESET RESET
VHC244
LV
CC
4.7 k
Ω
VHC244
CLK IN
X1
X2
Input
Output
Open
IE-784225-NS-EM1
X1 mounted clock
Multiplier
ALS157
JP1
Multiplier
ACT86
RZT025P
ALS157 (multiplier selection)
Remark The multiplier can be selected by switch 4 of the DIP switch (SW3).
When the multiplier is not selected, the IE system is supplied with the input frequency unchanged.
When the multiplier is selected, the IE system is supplied with a frequency 2 times that input.
Be sure to observe the caution concerning emulation of the slew-rate clock in 3.4.4 .