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CHAPTER 5 CPU ARCHITECTURE
107
Figure 5-11. General Register Configuration
(a) Absolute Name
(b) Function Name
R7
R6
R5
R4
R3
R2
R1
R0
8-Bit Processing
16-Bit Processing
RP3
RP2
RP1
RP0
BANK0
BANK1
BANK2
BANK3
15
0
7
0
F E F F H
F E F 8 H
F E F 7 H
F E F 0 H
F E E F H
F E E 8 H
F E E 7 H
F E E 0 H
H
L
D
E
B
C
A
X
HL
DE
BC
AX
BANK0
BANK1
BANK2
BANK3
15
0
7
0
8-Bit Processing
16-Bit Processing
F E F F H
F E F 8 H
F E F 7 H
F E F 0 H
F E E F H
F E E 8 H
F E E 7 H
F E E 0 H
Содержание 78014Y Series
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