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CHAPTER 1 OUTLINE (
µ
PD78014 Subseries)
45
1.7 Block Diagram
Remarks
1.
The internal ROM and RAM capacities depend on the product.
2.
Pin connection in parentheses is intended for the
µ
PD78P014.
TO0/P30
TI0/INTP0/P00
TO1/P31
TI1/P33
TO2/P32
TI2/P34
SI0/SB0/P25
SO0/SB1/P26
SCK0/P27
SI1/P20
SO1/P21
SCK1/P22
STB/P23
BUSY/P24
ANI0/P10 to
ANI7/P17
AV
DD
AV
SS
AV
REF
INTP0/P00 to
INTP3/P03
BUZ/P36
CLOCK OUTPUT
CONTROL
PCL/P35
BUZZER OUTPUT
INTERRUPT
CONTROL
A/D
CONVERTER
SERIAL
INTERFACE 1
SERIAL
INTERFACE 0
WATCH TIMER
WATCHDOG
TIMER
8-bit TIMER/
EVENT COUNTER 2
8-bit TIMER/
EVENT COUNTER 1
16-bit TIMER/
EVENT COUNTER
78K/0
CPU CORE
ROM
RAM
V
DD
V
SS
SYSTEM
CONTROL
EXTERNAL
ACCESS
PORT6
PORT5
PORT4
PORT3
PORT2
PORT1
PORT0
P00
P01 to P03
P04
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
AD0/P40 to
AD7/P47
A8/P50 to
A15/P57
RD/P64
WR/P65
WAIT/P66
ASTB/P67
RESET
X1
XT1/P04
X2
XT2
IC
(V
pp
)
Содержание 78011BGC AB8 Series
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