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NCR PC4I, Техническое описание

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Содержание PC4I

Страница 1: ...Personal Computer PC4i Technical Reference Manual...

Страница 2: ...w technology components software and firmware become available NCR Corporation therefore reserves the right to change specifications without prior notice All features functions and operations describe...

Страница 3: ...video RAM The NCR PERSONAL COMPUTER MODEL 4i is equipped with Centronics and RS 232 C interfaces as standard These are accessed at the rear of the computer without any dismantling Full access to the...

Страница 4: ...formation and communication system Videotex is administered under the auspices of the post and telecommunications authorities of a number of countries The Videotex version of the NCR PERSONAL COMPUTER...

Страница 5: ...r Supply 1 22 Monochrome Systems 1 22 Color Systems 1 23 Specifications 1 25 Alternate Main Processor Board 1 26 CHAPTER 2 Programmable Intelligence 8088 8087 Co ordination 2 3 Programmable Interval T...

Страница 6: ...ess System Integration 8237 Registers Command Register Mode Register Request Register Mask Register Status Register Temporary Register Current Address Register Current Count Register Base Address and...

Страница 7: ...17 Programming Hints 4 18 Interface Availability 4 18 Initialization 4 18 Transmitting Data 4 20 Receiving Data 4 21 Centronics Interface 4 24 Software Control 4 27 Status And Control Registers 4 27 C...

Страница 8: ...sk Controller Status 6 64 Fixed Disk Controller Diagnostics 6 66 Fixed Disk Format 6 67 External Fixed Disk Connection 6 68 1 2 MB Flexible Disk Drive 6 69 CHAPTER 7 The Screen Display Available Adapt...

Страница 9: ...isplay Generation Videotex Controller Character Sets 10 11 10 11 10 12 Standard Characters 10 12 Definable Characters 10 17 Character Attributes 10 28 Color Selection Color Layers Color Coding Color L...

Страница 10: ...ations 10 56 Diagnostics 10 57 Status Register 10 58 Adapter Initialization 10 59 Modem Interface 10 59 Video Interface 10 61 Switches and Registers 10 62 CHAPTER 11 Index APPENDIX A Hardware Rererenc...

Страница 11: ...NCR PERSONAL COMPUTER as well as expan sion boards offered by NCR The standard display unit is made up of the following parts Cabinet Power supply One or two flexible disk drive s or one flexible dis...

Страница 12: ...RS 2l2C PARALLEL ux DISK 600 r 1 6 0KB 1 MEMOAV EXPANSION I I 10 l 4 KB I t_1J 7 K 00 1 1 _ _j I GRAPHICS CONTROL UR 1 G APHICS CONTROL LE A 32KB 1 l XPANSION 10 64 K8 I 113271 1 111 I I ALPHA I I CO...

Страница 13: ...display with two flexible disk drives and 256K memory A 12 inch color display with one flexible disk drive and one hard disk drive and 256K memory A 12 inch color display with Videotex one flexible d...

Страница 14: ...ss The NCR 3277 model numbers are defined in Figure 1 2 1 4 Major Model Sub Model Voltage Frequency Language 11 12 NCR3 Z17 Monochrome CRT Color CRT 13 Videotex CRT Color 01 02 Single Flexible Disk Dr...

Страница 15: ...mmmed to produce a variety of signals at various intervals Accuracy is ensured by the Timer deriving its synchronizing signals by way of suitable frequency division from the system clock You can use t...

Страница 16: ...cessing This also means that memory must be refreshed at fixed intervals to prevent its contents from disappearing Fortunately you need not _ normally be concerned about providing refresh cycles as th...

Страница 17: ...RS 232 C each require the use of one of the six remaining connectors The NCR PERSONAL COMPUTER has the advantage that these three functions are interfaced separately to the main processor board thus m...

Страница 18: ...a o D CX D I f1 IIIUS OHTA 6266 DATA BUFFER L ij __ E I f n c CENTRONICS g 6 I IADR BUFFER l 0 j RS 232 C CWMNCATION n r CJ s n s CX n C CX 0 CX C I IAOR l BUFFER N U1 m A aJ 62 PIN 1 0 f CONNECTOR 7...

Страница 19: ...of more than one clock unit is enabled by the WAIT STATE LOGIC CHIP SELECT CS LOGIC converts address information into CS signals for memory and I 0 interface integrated circuits A DMA PAGE REGISTER a...

Страница 20: ...SYSTEM OVERVIEW lI 1 10...

Страница 21: ...nous Ser1al 1 0 SYSTEM OVERVIEW Clock Controller 256 KB Memory I 0 Bus Arbitration c a p 0 w E R CC G t J l 1 x DRIVE EJ EJGCJG c a t c J i B B E t EJ Coprocessor Programmable Interrupt Controller DMA...

Страница 22: ...summarizes the connector pin designations The following descriptions provide explam1tory notes to the control lines RESET DRIVE Output This signal is issued in response to a system reset It is synchr...

Страница 23: ...er IOW Output As for MEMW except that the selected address is to be understood as an address in the I 0 map IOR Output As for MEMR except that the selected address is to be understood as an address in...

Страница 24: ...8 CARO saECT 01 9 12V DO 10 GND IO CH ROY 11 MEMW AEN 12 MEMR A19 13 IOW A18 14 IDR A17 15 DACK3 A1B 16 DRD3 A15 17 OACK1 A14 18 DRD1 A13 19 OACKO A12 20 CLK A11 21 IRD7 A1D 22 IROB A9 23 IRD5 AB 24...

Страница 25: ...supplied to the microprocessor and other system components The high portion of the signal is 33 CARD SELECT Connected to slot 7 this signal must be supplied by any adapter connected to expansion slot...

Страница 26: ...cription of the Parallel Input Output Interface in Chapter 2 One or more jumper sw i tches are present on the ma i n pr ocessor board see Figure 1 7 The jumper switch block consists of either J5 or th...

Страница 27: ...f l DDQQDDDD 256 KB Switch 4 Off C Alpha Controller Switch 5 Off DODOQQDD Switch 6 Off 1 2 J S 6 7 8 Graphics Controller Switch 5 Off DDDD DD 40 X 25 Switch 6 On Switch 5 On 1 l l 4 S 6 7 8 Graphics C...

Страница 28: ...sertion on the memory expansion board K101 K100 upgrades the system memory capacity by 64 KB Installing the maximum 5 kits K100 creates a total system memory capacity of 640 KB that is up to but not i...

Страница 29: ...mory Expansion Configuration Switches NOTE Systems with the Alternate Main Processor Board allow memory expansion up to the maximum 640 KB on the main processor board itself A separate expansion board...

Страница 30: ...TEM including BIOS interface STANDARD RAM CAPACITY 6 x 64 KB RAM EXPANSION VIDEO MEMORY GRAPHICS DISPLAY optional VIDEO DISPLAY CHARACTER DISPLAY RESERVED CHARACTER DISPLAY VIDEO MEMORY GRAPHICS ADAPT...

Страница 31: ...38F 3C0 3CF 3D0 30F 3ED 3E7 3F0 3F7 3F8 3FF OMA Controller 8237 Programmable Interrupt Controller 8259 Programmable Interval Timer 8253 Parallel Input Output Interface 8255 OMA Page Select Register N...

Страница 32: ...se in primary Strappable for the nominal mains supplies of 120 V and 240 V total permissible range 107 V to 257 V DC outputs max power output 133 W 5 V 12 V 5 V 12 V 15 A max 5 5 A max 0 3 A max 0 25...

Страница 33: ...v Ground from the N C Line J Line removed Neutral switch Connector Outputs Connector Auxiliary S Connector Power Switch Connection 2 and keyed Connector l Power Input Figure 1 13 Power Supply Connecti...

Страница 34: ...ntial supply deviation 50 for 1 2 cycle once every 10 seconds 2 Ground Connector 3 1 85 Vl C CRT Supply 14 Ground 13 Power Good 12 12V 11 sv 10 5V 9 tSV B sv Connector 7 Ground Outputs 4 6 Ground 5 Gr...

Страница 35: ...USA Canada Europe Germany RADIO INTEIFERENa USA Germany Height 368 11111 19 mm 34 mm front beck 22 68 kg 2 04 kg Width 460 mm 520 11111 Streppeble 120 220 230 240 range 1D7 257 60 Hz 49 61 Hz Depth 44...

Страница 36: ...ed use of VLSI components The layout of this board is shown in Figure 1 16 Asynchronous Serial I 0 Coprocessor Programmable lntervel Timer Flexible Disk Programmable Bus Dri 111 Cnntroller lnterupt Co...

Страница 37: ...MB flexible disk drive is installed This disables the flexible disk controller IC on the main processor board Coprocessor Switch 2 On i iiii Not Installed Coprocessor Switch 2 Off ii ffliffl Installed...

Страница 38: ...256K Switch 2 On Bank 2 64 K Bank 3 64K Serial Port Switch 3 On iiiffl Enabled Parallel Port Enabled Switch 4 On ffi i 1 Switch 5 On m I Figure 1 18 Configuration Switch 9flA The CPU is included in a...

Страница 39: ...OL NM CONTROL DECODER SYSTEM SWITCH WAIT STATE GEN SYSTEM OVERVIEW PARITY PARITY OUT GENERATOR PARITY IN PARITY CONTROL SPEAKER CONTROL SPEAKER KEYBOARD KBD INT CONTROL KBD PORT PRINTER DATA g PRINTER...

Страница 40: ...ed 3 Select group of registers for Port 62H 4 Enable RAM parity OJ I 5 Enable I 0 check DJ I 6 Enable keyboard clock 1J I 7 Clear keyboard 1J I D 1 2 3 D 1 2 3 I Display configuration switch SW1 5 11...

Страница 41: ...n switch SW1 4 5 II II 11 SW1 5 6 No of flexible disk drives 7 63 w D Enable parity DJ 1 Coprocessor installed 1 2 4 Not used 5 Lock system 1 6 7 Not used The VLSI unit also controls the parallel I 0...

Страница 42: ...C C C...

Страница 43: ...es for the small loudspeaker this is described in a separate Chapter The Programmable Interrupt Controller detects and manages service requests not only from selected peripheral devices but also from...

Страница 44: ...ystem bus Your NCR PERSONAL COMPUTER includes other programmable integrated circuits dedicated to more readily recognized peripheral control functions for example the serial I 0 CRT flexible and fixed...

Страница 45: ...sion by zero it can interrupt the CPU This is done by means of the non maskable interrupt writing to port OAOH with data MSB set enables the NMI resetting this bit disables the NMI The presence of the...

Страница 46: ...er either as a binary or a Binary Coded Decimal BCD operation Counting speed is determined by an external clock signal Counting is achieved by decrementation of a Counter from the value loaded down to...

Страница 47: ...crementing counter passes to zero OUT1 Memory Refresh line Initialization firmware requires only the lower 8 bits of the decrement Counter The value set is 12H which yields a signal period of approxim...

Страница 48: ...of the selected Counter are used as a 4 digit BCD counter If this bit is zero the Counter represents a 16 bit binary value MODE may be a binary value 0 5 in three bits The following modes can be imple...

Страница 49: ...oes low A newly set Counter value comes into effect after the next OUTput pulse Square Wave Generator Mode 3 As Mode 2 except that OUTput remains high for the first half of the count and goes low for...

Страница 50: ...ne Shot C L O C K I C L O C C J I I 1 1 t w o GAU tl___ _ J OUTl UT IIHlUUIU TI f II __ ________ A I A I KIDE 2 Reta Generator C l o t uuou ouo ut JI Fl S J MODE 4 Software Triggered Strobe w J J 0 OU...

Страница 51: ...ents have been read Reading the Counters Reading Counter registers requires some care in order not to disturb the counting process A Counter can be read directly or via a Counter Latch The former meth...

Страница 52: ...onstantly required at regular intervals Disadvantages arise when this need for information or the device requests for attention are only occasional and irregular Polling then means in many cases ineff...

Страница 53: ...f other interrupt types for software interrupts INT instruction Both uses of microprocessor interrupts are summarized in Chapter 3 and can be investigated further in the ROM BIOS assembly language lis...

Страница 54: ...ng address of the interrupt service routine for interrupt type 1O OAH is fetched from bytes 2AH and 2BH the IP value from bytes 28H and 29H INTERRUPT CONTROLLER HARDWARE ARD LOGIC The NCR PERSONAL COM...

Страница 55: ...he 8259A Programmable Interrupt Controller can be regarded as consisting of four logical aspects as shown in Figure 2 5 The cascade logic need not concern us in this description as the three cascade l...

Страница 56: ...nt active low from the microprocessor In 8088 mode the first of these acknowledgement signals places the identity of an interrupt in the In Service Register see below A second signal causes the PIC to...

Страница 57: ...stores interrupts which are currently being handled The bit for a particular interrupt is set as soon as the acknowledgement signal arrives from the microprocessor The corresponding bit in the IRR is...

Страница 58: ...of previous DCW2 The PIC is to place IMR on date bus Figure 2 B PIC Addressing Note These commends ere valid only if the CS line is active low If this line is high or if both RD and WR are active low...

Страница 59: ...the interrupt request line until the first acknowledgement signal for that interrupt has been received from the microprocessor In practical terms this means that the IR signal should be reset at the i...

Страница 60: ...se bits should be zero SM if set instructs the PIC to apply a special fully nested mode when PIC s are cascaded in a master slave configuration This ensures that servicing an interrupt from a slave do...

Страница 61: ...by the initialization firmware However you should bear these considerations in mind if you wish to use a particular interrupt request for a purpose other than its standard hardware function If this i...

Страница 62: ...it zero If an interrupt is currently being serviced the PIC checks whether the new interrupt request is of higher priority If this is the case the ISR bit for the new interrupt is set and the correspo...

Страница 63: ...y set this representing the most recently acknowledged and serviced interrupt Therefore a non specific EOI is all that is required A specific EOI is required in situations where your software has dete...

Страница 64: ...1 I 07 DB D5 D4 D3 D2 D1 DO vfa Port 1 1 OCW2 I R SEDI EDI D D Int Request 20H Figure 2 10 Operation Command Word 2 The significance of bits D7 DS in OCW2 is as follows R when set this bit instructs...

Страница 65: ...d interrupt request appears at IR3 and assuming no further unmasked interrupts appear at IR6 IR7 RO IR1 and IR2 the new interrupt at IR3 will be dealt with after IR6 has been serviced Non specific EOI...

Страница 66: ...rs OCW3 is illustrated in Figure 2 12 D7 DB D5 D4 D3 02 D1 DD I via Port DCW3 D SME SM D 1 PO RREG REG 2DH Figura 2 12 Operation Command Word 3 SME if set tells the PIC to set or cancel a special mask...

Страница 67: ...the highest priority interrupt waiting for service is represented as a 3 bit binary value in D2 DO RREG and REG enable your software to read the PIC registers IRR and ISR To read one of these register...

Страница 68: ...noise on the IR lines r If a non valid interrupt request occurs the PIC recognizes it as an IR7 signal Your software for this interrupt type need only execute a microprocessor IRET instruction In thi...

Страница 69: ...ervice routines for timer type 8 and keyboard type 9 a software interrupt is issued type 1CH for the timer type 1BH for the keyboard The addresses placed by the ROM BIOS in the interrupt vectors for t...

Страница 70: ...s not overwritten by a subsequently loaded program The program consists of the following routines SETUP reads the initial clock time from the keyboard buffer NCR DOS system call in the form hh mm ss S...

Страница 71: ...hat the setup will still execute as a normal EXE file You can then retain a reduced nuber of paragraphs at the end of the setup process NEW IVEC exchanges the current vector entry for interrupt type 1...

Страница 72: ...ter alpha controller replace this value by OBOOOH CSEG SEGMENT ASSUME CS CSEG DS CSEG SS CSEG DRG 1DOH PUSH CS PDP DS XOR AX AX MOV e AX For use as segment override prefix when eddressina absolute mem...

Страница 73: ...Address byte following separator Until all 3 time units read Counts fractions of a second Inhibit interrupts while int vector is being written Set timer counter O for 19 ticks per second Timer operati...

Страница 74: ...orraat zero in video ma111ory MOV AL BH BCD hour MOV CL 4 Shift factor SHA AL CL Upper digit of hour now in 4 LSBs CALL SCAN MOV AL BH acm hour lower digit CALL SCAN Hour naw displayed MOV AL DAH rPr...

Страница 75: ...et attribute byte NOT AL XOR AL BBH And invert displ mode monochrome MDV ES DI AL Write attribute byte to screen INC DI RET Write address of user interrupt serv ce routine into vector for nt type 1CH...

Страница 76: ...A CS from storage Lowest address in int vector of entry for int type Restore former IP Restore former cs r Interrupt Service Routine maintaining end displaying s user clock using BCD arithmetic 1 ISR1...

Страница 77: ...MOV AL TICK INC AL CMP AL 19 JZ SECUP MOV TICK AL JMP ISREND MOV TICK 0 MOV AL SECOND CALL INCTIM CMP AL BOH JZ MINUP MOV SECOND AL CALL SEETIM JMP ISREND MOV SECOND O MOV AL MitlJTE CALL INCTIM CMP...

Страница 78: ...Check for total clock rollover Seconds end minutes already zeroed Restore statue of interrupted program Data segment now refers to NCR DDS program setnent of celling program MDV SS CS SSSTORE MDV SP...

Страница 79: ...all OAH Lowest int vector address used by int type 1CH user timer Storage for int vact IP cs Byte storage for BCD values II II values read from keyboard Single Q OCK pulse counter Beginning of graphic...

Страница 80: ...usted so that the interrupt return is to the routine from which the SR for INT 9 not 1BH was activated The considerations regarding CPU segment registers and NCR DOS program segment protection in the...

Страница 81: ...ES BX CS CS of new ISA DEC BX DEC BX MDV AX OFFSET ISR1 B IP of new ISA MOV ES BX AX now written to int vector MOV IVECIPJ CX MOV IVECCS DX RET Interrupt Service Routine to invert video display monoc...

Страница 82: ...PDP SI PDP ox PDP DS PDP ex PDP BX PDP AX STI IRET 2 40 to address video memory Offset of first attribute byte Invert it and write it back Point to next attribute byte Jump if last attribute byte not...

Страница 83: ...i ii iii iii i iii i VECT1B IVECIP IVECCS DBASE SSSTORE SPSTORE CJWNSTACK DW DW DW ow DW DW DW DOSCH D 0 OBBOOH 0 0 16 DUP STACKTDP DW 0 CSEG ENDS END lowest int vector address used by int type 1BH Ct...

Страница 84: ...sing the command register the other three for 8 bit parallel data I 0 to and from the system data bus These data ports are designated PA PB and PC They can be regarded as 3 separate groups each with 8...

Страница 85: ...is input port 3 PC bits 4 7 D output 1 input 2 D select Mode 1 for PB 1 select Mode 2 for PB Mode 3 not possible for PB 1 D PB is output port 1 PB is input port D PC bits 0 3 D input 1 output Figure 2...

Страница 86: ...a 1 1 I D I 0 1 a 1 1 I I 0 I D 1 1 1 D I I I 1 1 1 1 I I I I Figure 2 15 Mode 1 Combinations Mode 2 In this mode of operation only two I 0 groups are possible as the PC lines are used for control pur...

Страница 87: ...ter PC3 INTR for PA PCO INTR for PB Output PC7 OBF for PA PC1 OBF for PB PCB ACK for PA PC2 ACK for PB PC3 INTR for PA PCO INTR for PB If INTE is set this signal s triggered by the STB rising edge and...

Страница 88: ...Mode 2 Control Signals Mode 3 PC5 PC7 1 0 PA can be used as an 8 bit bi directional data bus using the control signals shown in Figure 2 18 In Modes 2 and 3 PC lines not dedicated to control function...

Страница 89: ...ommand 1 denotes Mode selection 6 5 Not used 4 3 3 bit binary value 0 7 indicating which 2 PC Line is to be set reset 1 D D reset Line DJ 1 set Lina 1 Figure 2 17 Mode 3 PC Line control OBFA A riNil P...

Страница 90: ...ollowing 2 bit binary values concerning the flexible disk drive mainboard memory and display configurations can be read from port PC Display controller type at switching on 1 graphic display 40 x 25J...

Страница 91: ...y Check PBS Enable 1 0 Channel Check PB6 Hold Keyboard Clock Low PB7 H J_h Clear Keyboard Low Select Kevboa1d Data onto PA 0 7 I PC Bit Meaningo 162Hl Pon PC Bit Moaningo t62H Pon 1Part PB Bit 3 Low P...

Страница 92: ...part of its program Obviously the CPU cannot make use of the busses for read write operations while the DMA transfer is in progress but it can still perform internal arithmetic as well as processing i...

Страница 93: ...ice during its idle cycle This allows the CPU to use the bus system and program the DMA controller RESET Input Clears the Command Status Mask Request and Temporary registers described in later section...

Страница 94: ...ss which are strobed into an external latch by means of the ADSTB signal OR Input Output In the idle cycle this is an input control signal used by the CPU to read the control registers In the OMA acti...

Страница 95: ...from the CPU Assuming the request line is not masked and is of adequate priority a DREQ input to the DMA controller results in assertion of the HRQ signal HLDA is the acknowledgement signal from the C...

Страница 96: ...written if this flip flop is in a zero condition the byte on the data bus represents the 8 LSBs of the word otherwise the data byte is the 8 MSBs The 16 bit registers are shown in Figure 2 22 An addi...

Страница 97: ...end Current Count 2 IN 6 Read Currant Address 3 ll lT 6 Write Base end Currant Address 3 IN 7 Read Current Count 3 OUT 7 Write Base end Current Count 3 Figure 2 22 8237 16 Bit Programmable Registers I...

Страница 98: ...d in the section DMA Timing in this Chapter If compressed timing is selected WS selects late 0 or extended 1 write selection PRTY is the priority scheme selection bit Fixed priority bit zero means tha...

Страница 99: ...on Select I I Figure 2 24 OMA Mode Register Transfer Mode is a value in 2 bytes specifying Single Transfer 1 Block Transfer 2 or Demand Transfer 0 A value of 3 would denote an 8237 cascade configurati...

Страница 100: ...place following an End of Process or Terminal Count condition During Auto Initialize the original values of the Current Address and Current Count Registers are restored using the values held in the Ba...

Страница 101: ...ts sets or clears the mask bits for Channels 0 3 according to the status of bits 0 3 respectively Bits 4 7 are don t care A Clear Mask Register command allows all four OMA requests In addition to thes...

Страница 102: ...is register is a running record of the address used for the byte currently being transferred This address value is incremented or decremented in accordance with bit 5 of the Mode Register after each b...

Страница 103: ...atically set to the values of the Current Address and Current Count Registers when the latter are programmed by the CPU It is not possible to read the Base registers under CPU control DMA TIMING The F...

Страница 104: ...MMABLE INTELLIGENCE c tu ____ ___ au ADSfe NO NJ 1 i I f DO O IIS YA Ll x ADCNllll f ALID DACO ioR iiiia iawiiiiiiii _ _ _ _ _ _ __ _ _ _ _ _ _ _ OC D D_ I S S N ll 1 lllll ll F gure 2 28 OMA Transfer...

Страница 105: ...x VALID C ft O A0Y _ _ _ __ __ _ _ _ __ J Figure 2 29 OMA Compressed Transfer C ADSTI ________ _______ A0 A7 ___ 0_0A_E_ss_ _ _ 0_ __ X ____ _00_ _Es_s_v _u_0___ 010 017 IN OUT iffiiii iiiiiw I rn EI...

Страница 106: ...OMA controller to address random access memory during the refresh cycles Because of the importance of these refresh cycles they are accorded the highest priority OMA Channel 0 in the fixed priority lo...

Страница 107: ...8 OUT 43H AL The next instruction loads the refresh divisor into Timer 1 so that an output signal occurs every 15 1 microseconds MDV AL 12H OUT 41H AL 2 Perform a DMA controller Master Clear the value...

Страница 108: ...e DMA controller is dedicated to servicing I 0 operations requested by the flexible disk controller on the main processor board This section illustrates OMA controller programming for the flexible dis...

Страница 109: ...access memory at locations offset to the beginning of the first 64 KB boundary from absolute address 10000H onwards DMA pages are described in the next section 3 You should now ensure that the first l...

Страница 110: ...apparent limitation your NCR PERSONAL COMPUTER includes an LS670 4 by 4 register file of which the RA and RB input lines are connected to the DMA controller see Schematics in Appendix A The LS670 RA...

Страница 111: ...logic it is important to note that the 64 KB memory blocks thus selected are separated from one another at multiples of 64 KB starting from the lowest absolute machine location It is not possible to...

Страница 112: ...C C...

Страница 113: ...Othe r routines largely dedicated to di rectory and file management a re supplied when the disk ope rating system is loaded Access to these routines is fully described in the NCR DOS programme r s inf...

Страница 114: ...d within the ROM BIOS ISRs for the Keyboard type 9 and Timer O type 8 interrupts respectively For the most part the ROM BIOS interrupts provide rou tines essential to the basic hardware functions of t...

Страница 115: ...return parameters are included for ROM BIOS interrupts Interrupt types 0 4 are dedicated to CPU functions Apart from type 2 NM the sources of these interrupts are common to all 8088 systems and cannot...

Страница 116: ...f the CPU Trap Flag ie set 2 Non maskabla Interrupt The ROM BIOS ISA checks whether the cause is RAM parity or external The ISA is concluded by a courtesy message and CPU Halt 3 Breakpoint This interr...

Страница 117: ...bit flags DB at 419H DW at 41AH DW a t 41CH 4 wait toggled 5 nllll depressed 6 caps depressed 7 ins depressed Keyboard Buffer at 41EH sae BIDS Data Areas A Reserved B Hardware interrupt for serial I...

Страница 118: ...9 640 x 400 graphics color Return screen cleared screen data areas initialized see next section AH 1 then set cursor style according to value CH top scan Line CL bottom scan Line Return DW et 460H ex...

Страница 119: ...0 6 in Qt value 0 199 raster pos modes 8 9 in C X value 0 39 horiz pixel pos in BX value 0 319 639 approx AH 5 then select active display page according to AL new active display page minimum value 0 p...

Страница 120: ...ock of active page down one character row Parameters es for scroll up AH B then reed cherecter attr bute et cursor pos BH display page Return AL character AH character attribute char modes only AH 9 t...

Страница 121: ...t foreground palette BL 0 green red yellow or 1 blue cyan magenta Return DB et 466H copy of CRT controller Color Select Register color sslected AH OCH then writs graph dot in active display paga AL do...

Страница 122: ...one Line if end of page AL character to write 7 B OAH ODH ere interpreted es commends not characters BL foreground color graphics Return character written AH OFH then get current video state Return A...

Страница 123: ...rs 5 format track AL no of sectors ES segment of buffer BX offset of buffer DL drive Cl 3 DH head 0 1 for read write CH track 0 39fi9 CL sector 1 8 9 15 verify format disk parameter table pointer see...

Страница 124: ...e O 1 1 D 7 DD 1 150 0 1 odd 1 2 1 1 8 D 1 D 300 1 D none D 1 1 BOD 1 1 even 1 D D 1200 1 D 1 2400 1 1 D 4800 1 1 1 9600 DX serial COM1 or COM2 device Dor 1 Return AH Line Status bit flags 7 timeout B...

Страница 125: ...device Return AL character AH bit flag 7 timeout AH 3 then read statue DX aerial COM device Return AH Line Statue see above J Modem Status see above I_ 15 Reserved 16 Read Keyboard Flags not restored...

Страница 126: ...urn 1 initialize interface 2 read statue only DX 0 1 2 or 3 1 of 4 printer base ports 0 takes base port fran OW 406H 1 OW 40AH 2 3 AH statue bit flags 7 buey 6 acknow ledge 5 out of paper 4 select 3 e...

Страница 127: ...nterrupt type 9 key depressed service Used by disk operating system 1C User timer interrupt always issued during service of interrupt type B Timer DJ 1D Contains segment offset address of the beginnin...

Страница 128: ...selection DB Final sector number DB Gap Length GPI DB Data Length DTL DB Length of format Gap 3 DB Format filler byte DB Head settle time DB Motor start time 1F Contains segment offset of graphics cha...

Страница 129: ...s not used to refer to code therefore en interrupt of this typemust not be issued The table is built up as follows 42 5F BD 7F BD FO F1 FF 1M Maximum number of cylinders DB 11 11 11 heads OW Cylinder...

Страница 130: ...aration type DB DW or DD Type Location Abaoluta Hex DW 400 DW 402 DW 404 DW 406 DW 408 DW 40A DW 40C DW 40E DW 410 3 18 Daacrtptton Basa port addresses for up to 4 serial I 0 interfaces Base port addr...

Страница 131: ...3 always sat 2 always sat 1 1 serial monitor installed D always set Reserved Memory size in KB Reserved Keyboard Flag 1 sea Interrupt 9 Keyboard Flag 2 sea Interrupt 9 AL tsrnata keypad buffer Keyboar...

Страница 132: ...O int type 8 Flexible disk operation status bits 0 command error 5 FDC failure 7 timeout 3 and O both set can indicate OMA error straddled 64 KB boundary Storage of up to 7 bytes from FDC Result Phas...

Страница 133: ...ffset pointer to the first byte of code of initialization routines contained in ROMs on adapters not included on the main processor board see section System Initializaion Segment value is the higher w...

Страница 134: ...indicator word value 1234H if reset in progress Fixed disk data area used during service of int 13H Timeout counters for up to four parallel printer channels Timeout counters for up to four serial I 0...

Страница 135: ...51D CDDD0 C7FFF CDDDD EFFFF CBDDO CCFFF FDDDD FFFFF THE OPERATING SYSTEM Daacrtptton Printer status values D not busy no error 1 busy DFFH error Single drive status A or BJ Reserved ROM expensi on Fix...

Страница 136: ...at machine address OCBOOOH If the identifier is not found that is if no ROM with this identifier is installed on an adapter the next attempt to find this identifier is made at the machine address OC88...

Страница 137: ...stalled in drive A the fixed disk ROM code re writes the interrupt vector for type 13H so that it points to boot loading routines on the fixed disk adapter ROM The most immediate effect of this is tha...

Страница 138: ...C 0 C...

Страница 139: ...l DLC interface is described in a separate Chapter The following cables relating to the RS 232 C serial and Centronics parallel interfaces are available K120 Centronics K121 RS 232 C Printer K122 RS 2...

Страница 140: ...21 Not Used I 22 Ring Indicator I 23 Not not provided with all I 24 Used main processor boards I 25 RCV a Data Figure 4 1 RS 232 C Pin Configuration The RS 232 C interface is programmable by means of...

Страница 141: ...s OUT2 INTRPT NC A ADS CSOUT ODIS DISTR 0 I I I I I Data bus buffer Select and control logic Receiver section Transmitter section Modem control and status logic I I I I L j t t Interrupt enable and I...

Страница 142: ...rking condition 12 CSO I ALL 3 Chip Select Lines must be active in 13 CS1 I order to select the 8250 14 CS2 I 15 8AUDOUT O I 16 XTAL1 17 XTAL2 18 DOSTAi I 19 DOSTR I 20 Vss 21 DISTAi I 22 DISTR I 4 4...

Страница 143: ...ignals during throughout an 8250 operation A1 28 AO 29 System addrese bus lines selecting an 8250 internal register No connection 30 INTRPT Output goes high whenever an enabled O interrupt is imminent...

Страница 144: ...rming that a ringing signal ie being received by the external device 40 Vee 5 Vdc supply Figure 4 3 8250 Signals 3 of 3 PROGRAMMING THE SERIAL RECBIVER TRANSHITTBR The 8250 converts parallel data to s...

Страница 145: ...ptional Second RS 232 C Interface 3299 K301 which must then be strapped to COM2 A separate hardware interrupt is dedicated to the second serial interface see Chapter 3 Figure 4 4 shows the structure o...

Страница 146: ...eive Transmit Data Interrupt ID Register port 3FAH Bit 7 6 5 4 3 2 1 0 0 0 0 0 0 Interr ID Pending I I Line Control Register port 3FBH 7 6 5 Divisor Set Stick I Latch Break Parity I 4 Even Parity Bit...

Страница 147: ...g Parity Overrun Data Interr Ready Nod Status Register port 3FBI Bit 7 6 5 4 I 3 2 1 D RLED RI DSR CTS DRLED TERI DDSR DCTS Figure 4 4 8250 Control Status Registers 2 of 2 Interrupt Enable Register If...

Страница 148: ...ine Status I Parity error or I Framing error or I Break Interrupt I Second 21 Data Receiver date Reed Receive I available Buffer Register I Thi rd 11 Transmit Transmit Holding This register read I I R...

Страница 149: ...Receive Buffer Transmit Holding Register 3F8H and Interrupt Enable Register 3F9H are selected Modem Control Register Bits 0 3 set force high the 8250 output lines DTR RTS OUT1 and OUT2 respectively B...

Страница 150: ...indicates that the register is idle Hodea Status Register Whenever bit O 1 2 or 3 is set a Modem Status interrupt condition is asserted see Figure 4 5 Bits O set indicates that the CTS line has change...

Страница 151: ...errupt System In the diagnostic mode receiver and transmitter interrupts are fully operational The Modem Control interrupts are also operational but the interrupts are now derived from the four least...

Страница 152: ...X x AJ Al At _ _ YALIO L x OJ cs Cit CIGUT DDIT _ _ _ _ _ _ _ _ ___ x rn x ___ 1 n I Diiiiiio1n DATA V ALIIOATA Gt DJ r Figure 4 6 Read Cycle WJDDijy n n n n n 1 11 LJ LJ U U LJ L llilDDiiT 1 21 AUD O...

Страница 153: ...CSOUf oisfii DISTR X ACTIVE X I o os f R DOSTR ODIS DATA B Do D1 Figure 4 8 Write cycle m U U 1r ICLU ir SAl1PLE CLK SAMPLE CLK IITIIUIUPl DATA IUADT 011 RCYllllllU _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...

Страница 154: ...IUI DOSTR DOSTR iJ IWR Ttlll nm _ D1Ull l1 Y2 n u I _ DISTR llSTR r _ IRD IA __ OOSTR OOSTA J IWAHCRI ATS OTA OUT DUT2 CTS OSA ALSO INTERRUPT Figure 4 10 Transmitter Timing ___ ____ oisfii tllSTA r r...

Страница 155: ...es are as set out in Figure 4 12 Where the integer nature of 16 bit binary counting results in a negligible deviation from the nominal baud rate this is indicated in the rightmost column Noa naL baud...

Страница 156: ...n Interrace Availability This examination of your system configuration checks for the availability of a serial I 0 interface as COM1 base port 3F8H or COM2 base port 2F8H according to the base port re...

Страница 157: ...write it this time with the Divisor Latch bit zero so that the port COM can transmit receive data and COM 1 addresses the Interrupt Enable Register MOV DX COM 3 IN AL DX Read Line Control Register XO...

Страница 158: ...CX TIMEOUT MOV DX COM B Point to Modem Status Register TIME1 IN AL DX AND AL 3DH Blank out ell but bi ts 4 CTSJ and 5 DSR CMP AL 3DH JZ MODRDY Jump if device ready LOOP TIME1 Otherwise check again unl...

Страница 159: ...d Register is already known to be empty No further status checks are required SEND MDV DX OOM MDV AL AH OUT DX AL Refer to Transmit Holding Register Receive Buffer Character assumed in AH Finally do n...

Страница 160: ...t shifted into the Receiver Buffer Again a timeout condition or alternatively some kind of user keyboard break check can be applied DATCHK TIME4 MOV CX TIMEOUT KIV DX COM 5 Data Ready bit is IN AL DX...

Страница 161: ...2 framing 3 error and break 4 bits Jump if any error or break The valid character can now be read from the Receiver Buffer Do not forget to provide suitable handling routines for MODXRDY and ERROR MOV...

Страница 162: ...e computer are set out in Figure 4 14 The pins are capable of sourcing 2 6 mA and sinking 24 mA Control data comprises the following lines STROBE AUTO INIT SELECT INPUT The pulse of at least 0 5 micro...

Страница 163: ...ead Status V Read ControL Write Control I Control latch n _ Data latch Steady state f 4 lines Status 1 10 Bus I Status 2 11 buffer _ Status 3 12 I Status 4 13 _ Status 5 15 Driver J TTL Buffered lines...

Страница 164: ...ed This signal is used by printers to denote an out of paper condition When this signal is active the device cannot receive data With printers this signal is active under the following circumstances d...

Страница 165: ...o read data from the Centronics interface it is first necessary to transmit the appropriate control information via port 37AH Data can then be read via port 378H Status reading is via port 379H Status...

Страница 166: ...AL 000011000 Reset printer INIT ClJT OX AL Here auto Line feed is disabled The following routine prints one character assumed to be available in AL Supply a TIMEOUT value suitable for your printer and...

Страница 167: ...eout examination described in the previous section is also applied The BUSY line status is constantly changing because the microprocessor is trying to output data faster than the printer can read it T...

Страница 168: ...You will notice that a single operational change of state can produce more that one status change This is due to transitional signal conditions POAT PSTAT PCONT FLAGSa TIMERR CR LF TIMEOUT 4 30 ED U...

Страница 169: ...ES1 SCRNMES STATCHK AH AH SOH NEXTCH PRTLOOP Notify timeout on screen Full status analysis Take next char in ASCII sequence Repeat printer iteration i ndef i ni te Ly STATCHK Analyse status CALL ROSTA...

Страница 170: ...haracter in output buffer INC DX Point to status port MDV CX TIMEOUT IN AL DX Reed status TEST AL 100000008 Examine BUSY JNZ STROOE LOOP WAIT2 MDV AL TIMERR JMP PRINTED Otherwise Loop until timeout MD...

Страница 171: ...B BUSY ACK DB CR LF DB DB CR LF STATLN2 DB CS83 ENDS END _ PRINTERS AND COMMUNICATIONS Display error message on screen using NCR OOS fuction call 9 display string up to Entry address of string in DX O...

Страница 172: ...C C...

Страница 173: ...it the requested data after which it returns to the receive mode Transmission speed is 48000 bi ts per second The maximum advisable length of cable in the entire network is 3600 metres 12000 feet The...

Страница 174: ...oscillator Figure 5 3 illustrates the integration of this controller in the NCR PERSONAL COMPUTER CONTROLLER Pll CORFIGURATIOR Figure 5 4 illustrates the pin connections of the DLC integrated circuit...

Страница 175: ...QJ QJ u rtl QJ DS 3 cc Cl DS 7 Reset eset C 0 I u UI u UI Addr AO A7 QJ QJ A0 A7 i C Cl UI i i Cl c 0 Cl u z DLCINT IOR u 0 TDM C IOW u TINT 0 Clock BIOR IC 0 RD C Int 0 0 BIOW WR u RDM B02 a I 0 CHR...

Страница 176: ...5 Volt D 6 IRQ 2 D 5 B 5 A 5 D 4 DRQ 2 D 3 12 Volt D 2 GND D 12 Volt D 0 B 10 A 10 I 0 CH ROY AEN IOW IOR B 15 A 15 DACK 1 DRQ 1 Clock B 20 A 20 A 9 A 8 A 7 IRQ 3 B 25 A 25 A 6 DACK 2 A 5 T C A 4 A 3...

Страница 177: ...r that the DLC controller requires attention Jumpers are factory set to issue IRQ3 Figure 5 2 The interrupt line is held high until it is acknowledged by the microprocessor IOR Input Pin B14 I 0 Read...

Страница 178: ...9 5 Pin B9 10 Pin B7 Pins B1 B10 B31 SOFTVAU CONTROL The interface address lines are decoded as follows IN 380H Data Receive Hold Register OUT 380H Data Transmit Hold Register IN 381H Status Register...

Страница 179: ...pected from the system bus In DMA mode the controller internally resets this bit when the transmission is complete Under direct microprocessor control of data transfer this bit is reset when a Transmi...

Страница 180: ...is transferred under microprocessor I 0 control DIAG Setting this bit causes the integrated circuit to carry out internal diagnostics In transmit diagnostics the output lines Ta and Tb are disabled Tr...

Страница 181: ...r command The condition was recognized during the last byte transfer in a microprocessor I 0 sequence FCS ERROR Frame Check Sequence Error After a complete frame has been received the received frame s...

Страница 182: ...it 2 A DLC controller interrupt sets this bit 4 ms timer interrupt Reflects DRQ IRQ jumper selection 0 DRQ2 and IRQ2 1 DRQ1 and IRQ3 Unique Address Register This register identifies the NCR PERSONAL C...

Страница 183: ...o the type of transmission required When the Command Register hes been written the transmission sequence is started end en interrupt is generated 2 Transmission circuits ere enabled following servicin...

Страница 184: ...DLC INTERFACE Interruot N Out ut 5 12 Interrupt Service Routine ISR Read Interrupt St tus Register DLC In terr y IRET Figure 5 8 CPU Transmit 2 of 2 y Timer In terr Polling Service Routine nX4msec...

Страница 185: ...med first 3 The receive commend starts by activating the receiver circuits First a valid addressed frame is searched for Upon detection an interrupt is issued indicating that a data transfer to the sy...

Страница 186: ...ue Addr R to device addr IR03 Only Secondary Corrun N Interru t Routine In N Interrupt Service Routine ISR DLC Interr IRET Tiir er In terr Polling Service Routine nX4rnsec Note The last data byte is n...

Страница 187: ...ansmission required If both TXFR end TXFLG are set Commend Register 11xx0DDD interfreme time will be filled with contiguous flags If TXFR is set end TXFLG is zero Commend Register 1DxxDDDD the frame i...

Страница 188: ...1 Command R Read Interrupt 0AH OMA Count T to FFH Comm N Interrupt Interrupt Service Routine SR Read Interrupt Status Register DLC In terr y y IRET Timer Interr Polling Service Routine nX4msec Figure...

Страница 189: ...ing AXA and accordance with the type of memory Address to be unique Address be ell Command RXB in receive required and with the ID DMA bit zero 5 After a valid addressed frame has been detected data i...

Страница 190: ...nique Addr R to device addr Only Secondary R to IDFFH Comm N Interru t Routine Input Interrupt Service Routine ISR Read Interrupt Status Register DLC Interr y IRET y Timer Interr Polling Service Routi...

Страница 191: ...ternal fixed disk drive 3282 1212 External fixed disk drive 3299 K725 Controller for fixed disk drives K702 makes use of the flexible disk drive controller incorporated in the system main processor bo...

Страница 192: ...After 15 s 6 ms 495 ms 100 ms 25DK bits sec MFM 250 mA average 900 mA peak 500 mA average BOO mA peak Figure 6 1 Flexible Disk Drive Technical Data Power connections to the flexible disk drive are il...

Страница 193: ...motor assembly frack 00 sensor assembly Clamp arm assembly DISK STORAGE DD Motor servo board Stepping motor MFD Control board DD Motor assembly Index sensor Head carriage assembly Figure 6 3 Flexible...

Страница 194: ...exible Disk Drive Streps CONTROL ABD DATA SIGNALS The flexible disk drives use the standard pin assignments as shown in Figure 6 5 Figure 6 6 shows the corresponding edge connector on the flexible dis...

Страница 195: ...Drive s 2 Drive s 0 14 IN Drive s 1 Drive s 1 12 IN Drive s 0 Motor On OJ 10 IN Index 8 OUT Drive s 3 6 IN Head Load 4 IN C NOTE All odd numbered p ns are signal ground Designations in parentheses ar...

Страница 196: ...isk Active high causes the head to move toward the outside of the disk Step Active low input signal to move the head in the direction specified by Direction Select Each step pulse is delayed by 6ms fr...

Страница 197: ...e I generator I Ready detector t 1 Spindle motor gate Direction Stepping motor_ __ Select control Step circuit I I L LVS ____ DISK STORAGE Track 00 Index Ready Write protect Stepping motor File protec...

Страница 198: ...I JI Read write head TP7 Low pass filter r o IAI AO IAI I I I I I WO I l Data latch WD Write data Differentiation amp TP10 Cl Cl I b Peak detector Tim RD I I Read data domain Output Erase driver Writ...

Страница 199: ...nstalled in the drive The drive inhibits writing and provides the write protect signal irrespective of the state of the Write Data and Write Gate signals Read Data Output signal containing composite c...

Страница 200: ...ss Timing 1 LJ I L J t 7 19 1 N I r BllO OS ir 1 l l s i r4 _________r j I f l 8 0 us j r II _ 4 1 I i uu rL I 4 I L J L Ji_ CO AlS I f 4f 150 CO 2500 lS 1 ______ ______J s l SO a r e d oad sotenoi 3C...

Страница 201: ...Ii sr zcu r 17 ff QAff HEAD SELECT I _ _ _ _ _ _ __ _ _ 200 p J s II e M C T L s I i sS o x j n r 1 I I I O J S _ I ao ss KA JC Figure 6 11 Read Initiate Timing INDEX LJ I 1 TO 5 5 MS 200 J O MS Figur...

Страница 202: ...iff DITA 1 G rf 0 J I _Jlc C Vuff C1JlCX u n I 0 0 1 J C L D Vant a oc ML I s IIT Cau _ Figure 6 13 MFM Write Pre compensation Patterns CI Oat l1lm01 L BIT c zu I 4 uS tlt j _I1____Sl____ t l uS KOK _...

Страница 203: ...e edge of the index pulse to the beginning Sync Field for the ID field address mark This gap allows for variations in Index pulse width speed variations and interchange tolerances between drives Pre I...

Страница 204: ...___ I I Luc s cor c _ E r1a1 1 0 or 1 9 02 means 512 bytes Scccm 1 I s c rr 2 I ccto 6 ll I llllca rtald ca G tpl S c 1 1 I D 3 T1ud 1 eld l Post nde x Cap 2 Pre Data Gap 3 re rD Gap 4 Pre Index Gap A...

Страница 205: ...ain Status Register OUT 3F5H Output up to nine commands to the command stack IN 3F5H Input one of up to seven results from the result stack including up to four 8 bit status registers The FDC can perf...

Страница 206: ...a byte from the FDC requires both these bits to be 1 The FDC in your NCR PERSONAL COMPUTER operates in DMA mode with the result that interrupt detection before reading individual bytes is not require...

Страница 207: ...process The FDC is in non OMA mode Thie bit is set only during execution phase in non OMA model Transition to zero indicates I execution phase hes ended I Indicates direction of date transfer between...

Страница 208: ...t set enables FOC 3 Bit set enables OMA request and FOC interrupts to be to I 0 interface Bit zero disables I 0 interface drivers 4 Turns motor of drive A on bit set or off bit zero 5 B 6 C 7 0 Figure...

Страница 209: ...mmands and their data are input in the correct order and that return informa tion is read completely even if elements of this information are not required p H A s E C 0 a n d E X a R e 8 u L t I DATA...

Страница 210: ...D Oa ETED DATA MT MFM SK 0 1 1 0 0 Command Codes 0 0 0 0 0 HOS DS1 DSO C Sector IO info H _______ prior to Com mend execution EDT GPL DTL STD _ _ _ _ ST1 ST2 C Date transfer between the FDD and main s...

Страница 211: ...t w w w w w w w w MT MFM D D D D D D D 1 D 1 D HOS DS1 DSO C H R r EDT GPL Command Codes Sector ID info prior to Com mand execution W DTL R R R R R R R Date transfer between the FDD and main system S...

Страница 212: ...02 01 DD lfRITE DB ETBl DATA MT MFM D D D D D D 1 D D 1 D tllS DS1 DSO c H R r EOT GPL DTL STD ST1 ST2 C H R N Command Codas Sector ID info prf or to Com mand execution Data transfer between the FDD a...

Страница 213: ...ID info w H prior to Corn w R mend execution 8 w N n w EDT d w GPL w DTL E Data transfer X between the FDD B end main system C FDC reads all of cy Linder a contents from index hole to EDT R STO Status...

Страница 214: ...ata Register Status info after Command execution H Sector ID info R during Execution N Phase RHIAT A TRAOC I I C d E X R e 8 u l t 6 24 W MT MFM D D 1 1 D O Command Codes I W D O D D D tlJS DS1 DSO I...

Страница 215: ...E Data compared X between the FDD a end main system R STO Status info 0 R R ST1 after Command e R ST2 _______ execution s R C u R H Sector ID info l R R after Command t R t execution I s I I__ IC I W...

Страница 216: ...w w w w w w w R R R R R R R MT MFM SK 1 1 0 0 1 Commend Codes 0 0 0 0 0 HOS DS1 DSO C Sector ID info H prior to Com R N EDT GPL STP mend execution Date compe red between the FDD end main system STD St...

Страница 217: ...d w GPL w STP E Date compared X between the FDD e end main system R STD Status info R R ST1 ________ _ _ after Commend e R ST2 execution B R C u R H Sector ID info L R R after Commend t R _________ N...

Страница 218: ...FDC I SPECIFY TUE 1 1 CI W I o I w I I w D D D O D D 1 1 SAT HUT ILT ND Command Codes I SENSE DRIVE S TAlUS I I I c I W I o o D D o 1 D a I Command Codes I I I W I D O D D O tlJS DS1 DSO I I I I I I I...

Страница 219: ...d of Track Gap Length DS stands for a selected drive number O or 1 When N is defined as OD OTL stands for the data Length which users er e going to reed out of or write into the Sector Otherwise DTL s...

Страница 220: ...I HD1 will be reed or written I Number IN stands for the number of I I data bytes written in a Sector I New Cylinder tlCN stands for new Cylinder I Number number which is going to be I reached as a r...

Страница 221: ...2 Status E information after e commend hasl ST3 Status 3 been executed This info is I available during the result I phase after command execution I These reg i stars are not to be I confused with the...

Страница 222: ...s performed they are not output to the data bus Figure 6 21 states factors affecting transfer capacity of a single read command NT Byte I Max Transfer Capacity Sector Bytae Sactor N I Nuaber of Sector...

Страница 223: ...o seconds Failing this OR in Status Register 1 see below is set Possible error conditions Failure to find the specified sector sets the ND flag in Status Register 1 In Status Register O bit 6 is set a...

Страница 224: ...tor 15 at Side 1 I C 1 I NC I R D1 I NC I 08 I Sector 8 at Sida 1 I I I I 1A Sector 1 to 25 at Side O I OF Sector 1 to 14 at Side O NC NC R 1 I NC I 08 I Sector 1 to 7 at Side o I I I I 1 1A I Sector...

Страница 225: ...mmand Other details as in READ DATA WRITE DELETED DATA As WRITE DATA except that a Deleted Data Address Mark is written at the beginning of the Data field READ ID This command returns the current head...

Страница 226: ...omplement arithmetic The operation is carried out for the specified track with automatic incrementing of R until the condition is fulfilled end of track is reached or a TC signal occurs If the scan co...

Страница 227: ...der has been located SE in Status Register O is set and the command terminated If the disk drive is not ready the NR flag in Status Register O is set and the command terminated This command does not i...

Страница 228: ...tion resulting from an FDC command 1 I Interrupt Code I I I Seek End 1 1 Cause I I e t 5 I e t s I e t 7 I I I_______________________I I O 1 1 Reedy Line changed I I I I I state either polarity I I___...

Страница 229: ...ive Code is a two bit binary value O A 1 B Bit 7 6 5 4 3 2 1 D Motor On D D 1 8 1 A 1 1 Drive Code Motor Off 0 0 D D 1 1 0 0 NOTE Motor Off is provided by the ROM BIOS eft r 1 r 1 c 1 rm entetion to z...

Страница 230: ...mand was started but was not success fully completed 07 1 and 06 o Invalid Command issue IC Command issued was never started 07 1 and 06 1 Abnormal Termination because during Commend execution the Rea...

Страница 231: ...eady I state and a Read or Write I commend is issued this flag I is set If e Read or Write I command is issued to Side 1 of I e single sided drive then I this flag is set HD This flag is used to indic...

Страница 232: ...s flag is set If the FDC is not serviced by the main system during data transfers within a certain time interval this flag is set Not used This bit is always 0 low During execution of READ DATA WRITE...

Страница 233: ...tects a write protect signal from the FDD then this flag is set MA If the FDC cannot detect the ID Address Mark after encoun tering the index hole twice then this fleg is set If the FDC cannot detect...

Страница 234: ...bit Cylinder flag is set when contents of C differs from that of m reg 03 Seen SH Flag is set when condition Equal Hit equal is satisfied upon Seen D2 Seen Not SN Flag is set when FDC cannot Satisfied...

Страница 235: ...es status of Ready signal from the FDD D4 Track D TD Bit indicates status of Track 0 0 signal from the FDD 03 Two Side TS Bit indicates status of Two Side signal from the FDD D2 Head HD Bit indicates...

Страница 236: ...disk controller interfaces the disk drive to the host processor All necessary buffers and receivers drivers are included on the Winchester disk controller board to allow direct connection to the driv...

Страница 237: ...DISK STORAGE DISK C PCB LED HEAD CARRIAGE ASSEMBLY C Figure 6 29 Fixed Disk Drive Components 6 47...

Страница 238: ...responding edge connector is shown in Pigure 6 32 Data in MFM format is transferred by means of a separate cable pin assignments and edge connector are illustrated in Figures 6 33 and 6 44 The input a...

Страница 239: ...20 IN READY 22 IN STEP 24 DUT DRIVE SELECT1 26 OUT DRIVE SELECT2 28 OUT DRIVE SELECT3 30 OUT DRIVE SELECT4 32 OUT _ DIRECTION IN 34 OUT Odd numbered connections are Ground Figure 6 31 Fixed Disk Contr...

Страница 240: ...13 MFM WRITE DATA 14 Gttl 15 MFM READ DATA 17 MFM READ DATA 18 GNl 19 Other connections ere Ground Figure 6 33 Fixed Disk Dontroller Drive Data Signals 037 003 i 1 r 1 2 6 1 400 4 50 I 350 I 1_ i I 15...

Страница 241: ...R W head to move with the direction of motion defined by the Direction In line Any change in the Direction In line must be made at least 100 ns before the leading edge of the step pulse The drive acc...

Страница 242: ...g cases 1 A recalibration sequence is initiated by drive logic 2 12 microseconds typical after the leading edge of a step pulse or series of step pulses 3 At power on or after a power interruption Tra...

Страница 243: ...tion 16 67ms nom to indicate the beginning of the track This signal is normally inactive and makes the transition to active to indicate Index Ready This interface signal when active together with Seek...

Страница 244: ...ured by pre compensation being active Data patterns which cause a large amount of bit shift have appropriate data bits shifted early or late with respect to the nominal bit cell position Bit shift com...

Страница 245: ...sec Typ Figure 6 37 Seek Timing DRIV L HO SEL i MFM VA LIO READ OAlA WRITE GATE r e s MAX 1HEAD SWITC HING i r 2snsMIN l_ 200ns TYP f BIT CELL 1 MAX I I s i r l f 50 150ns MFM WRITE DATA f Ul ____ I I...

Страница 246: ...Y I X 1 1 0 I WRITE CLOCK LATE I 1 0 0 0 I WRITE CLOCK EARLY I 0 0 0 1 I I x denotes don t care Figure 6 41 Write Pre Compensation Patterns IXED DISK CONTROLLER rhe fixed disk controller includes feat...

Страница 247: ...ance of the status bits read via port 321H Writing to this port effects a hardware of the hard disk drive system The value actually written is of no significance Reading port 322H returns in bit posit...

Страница 248: ...usy executing a command 4 ORQ DMA Bit set indicates that the controller is ready for a OMA transfer in the direction indicated by the bit I 0 5 IRQ Bit set indicates that an interrupt is pending B 7 N...

Страница 249: ...a second run of 10 retries after an intermediate return to Track 0 A non recoverable error aborts the command and reports the fact in the status return described later in this section The 3 bit value...

Страница 250: ...arameters Read ECC Burst Error Length Read Sector Buffer Write Sector Buffer Read Write long The following descriptions deal with these commands in detail Where values are required for the 6 byte comm...

Страница 251: ...leave tells the controller where the next logical sector is in relation to the current one the value 1 specifies that logical sectors are contiguous 2 specifies that the next logical sector is two sec...

Страница 252: ...Drive Head Cylinder Sector Block Count R1 Step This command functions as Command 08H except that sectors are written and not read SEEK Command Code OBH Specific parameters Drive Head Cylinder Sector...

Страница 253: ...inder 153 11 bit burst error length READ ECC BURST ERROR LENGTH Command Code ODH Specific parameters Drive This command is valid only after a correctable data error It transfers one byte indicating th...

Страница 254: ...detailed status information is returned in 4 bytes via Command 03H Read Status of Last Disk Operation After this command has been issued the four status bytes can be read via port 320H 6 64 Byte Bit...

Страница 255: ...ion could not be found due to en unmatched ID field or bed CRC Correctable Date Error A media error encountered while reeding was corrected by ECC This error notification is therefore essentially for...

Страница 256: ...ler Diagnostics As the result of an explicit command from the microprocessor one of three internal diagnostic commands can be performed by the fixed disk controller SECTOR BUFFER DIAGNOSTIC Command Co...

Страница 257: ...3 bytes of 00 2 A1 FE 3 1 byte 4 1 byte 5 1 byte B 2 bytes 7 3 bytes of 00 e 13 bytes of 00 9 A1 FB 10 256 bytes 11 2 bytes 12 3 bytes of 00 13 15 bytes of 4E 5 6 s C E R C C one of 32 sectors 7 8 9 1...

Страница 258: ...Pin I Signal 1 DIRECTION IN 19 MFM WRITE DATA 2 DRIVE SELECT2 20 GND 3 DRIVE SELECT1 21 GND 4 STEP 22 GND 5 READY 23 GND 6 INDEX 24 GND 7 HEAD SELECT1 25 GND 8 HEAD SELECTD 26 GND 9 WRITE FAULT 27 GND...

Страница 259: ...board Tracks per inch TPI Tracks per disk side Unformatted capacity Motor rotation speed Motor start time Head movement track to track Average seek time Latency time et 300 r p m Data transfer rate De...

Страница 260: ...two DS lines transposed IU When closed enables the IN USE signal at pin 4 of the control data connector This signal indicates that all the daisy chained flexible disk drives are in use under system co...

Страница 261: ...G High density HG Low density I II One of these straps must be installed RY DC Installed Density uses Rot Speed r p a I II High Low High Low 360 300 360 360 One of these straps must be installed pin 3...

Страница 262: ...___ t 1 0 10 tll Note The displacement of any bit position does not exceed tl2 from its nomlnal position When PLO separator is used with zero write pre compensation I Density Disk speedj 8 I t9 I tlO...

Страница 263: ...tt11 it o s Density D1sk Spe c t t4 ts I t6 High Orp i C l 1 bs 11s Max l s cm Ne rma l 360rpm J 1 bs I E i s a 3 J s lo lo s i o Ib 7 s er or al CCr ri Figure 6 52 Write Date Timing MFM u I I I I t7...

Страница 264: ...es are given in parentheses OUT 372H 3F2H Drive select command IN 374H 3F4H Main Status Register OUT 375H 3F5H Command Register IN 375H 3F5H Result input Otherwise I 0 addressing of the controller IC...

Страница 265: ...ed so that CPU access and CRT controller can access video RAM independently of one another AVAD ABLE ADAPTERS Only one version of the NCR PERSONAL COMPUTER contains the character display card as stand...

Страница 266: ...raphic display card with 16 KB video memory for an external monitor K141 Character display card with 4 KB video memory for an exteral monitor CAUTION Before connecting an external monitor you must ens...

Страница 267: ...ROUtll VSYNC 0 0 0 0 I Pin Internal External 9 6 I I I 1 I VIDEO LO GROUtll I G I 2 I HSYNCP GROUtt I R I 3 I RED RED I A I 4 I GREEN GREEN 0 I P I 5 I BLUE BLUE I H I 6 I INTENSITV I INTENSITY I I I...

Страница 268: ...x 25 setting if you are using the graphic display card lli Q II Monochrome Color graphics BO x 25 Color graphics 40 x 25 Figure 7 3 Display 9ivitch Settings CHARACTER SET The NCR PERSONAL COMPUTER dra...

Страница 269: ...is higher part of the table is retained in user memory even after the return to the parent process using the NCR DOS function call Terminate but Keep Process The exact location of the first 16 x 8 pat...

Страница 270: ...an nn nea ni i onr an in one 1 rien n nn no o nH 1n nno Bnn onnon on nnoononn OfJflflnOOO F nnnmmon nnnnnnnn RPi 0 fil88 nr r rirnn 01 e0nr m r r noo 81 r JfijR rinn_ ne R nnnnr 1 r n nr1l 10 RRri i R...

Страница 271: ...OD flrJ l 000 8 8 _888 nr1 ODO 100 Jf l JO r1 1C f 1 Q O 21 ooonnooo 00000000 onoloog DO 0 88 88 0 80 R 8non8 h8tl 888 d RoRogg nK n no rrnonrno 00000000 lOOoonoc qnor 1co 11011 JO JIJO llOCllJ IODO n...

Страница 272: ...nn nnrnri 4 onnnnonn glnR88R88 n nnoolo 88888 B o oog 8 88oi i o 0000 n 0 0000 0 Bn oR 8ff PR888 l TOO t 8 888 3C 00 00 g 88 8 C Jo 8 I 0 0 0 0 nrm o r 1 10 10 I 44 IA I 0 00 o B R BBB r H oo r ooo 11...

Страница 273: ...61 onoooon J 88888888 nr1oooogg 88 00 I no 88 8 g 8080 oo nr100 nnnrnnoo 6 0 000000 8080 000 8 J R 8 J o J 8R 88RR 00 DODOO 62 B 000 1000 O JOOOOOO nnoooooo 88Ri18tl88 AR 1 8 0 0 00 0 8 no n DO go ln...

Страница 274: ...88 91 888 8 8 8 o B 0 0 DO 000 BB 7A 8 1 86 BC ogo 8 oo o 0 0 0 r 92 888 r78 81 8 8 S8 0 88 0 8 III II 7C 8 O uu uu1 u 82 8 70 83 87 88 89 0 8888 88 80 BE BF 88 o og og 8 80 II I 80 8 1 93 94 95 Figu...

Страница 275: ...THE SCREEN DISPLAY C 96 97 98 99 9A 98 0 9C 9D 9E 9F AO Al 0 A2 A3 A4 A5 A6 A7 nnr AB A9 AA AB AC AD 88 8 8 C I i AE AF BC1 81 B2 83 Figure 7 4 The Main Character Set 6 of 9 7 11...

Страница 276: ...DOO D BA BB BC BO BE BF c 1 Cl C2 C3 C4 C5 OD 00 0 0 0 0 0 8 8 I 0 88 88 00 00 00 88 8 0 888 8 8 000 0 g 00000 88 88888 88 00000 C6 C7 CB C9 CA CB 00 0 1000000 00 s11 8 8 8 88 88888888 88 0 80 OD 8 0...

Страница 277: ...Oll gB JCJon ooo DIJBDDfl L 1 1 1 l lfl lfl RD 11100 00 r r f noooooo J IJ I I JOOUC r 8 I I flfif I 1 D 111 1J n11 8 8 D m 1a1 oo l ij 0 U0Jfl 10 0 n 1 1100 fJ 8 01 0 1 0 f ll o 0 flfi JODXJO 181JlJ...

Страница 278: ...00 000110 00 1 10jc nC1 og n ooo o uooocgo lllll1000 0 1 11 000 0 OCllJOOO r DXJ JCO 0 11 nnooo i iHR FB FE F3 gc111DC1DRS o88888ba tJOOOOODC o gnRPBn 111 1 n 10 o 1or 1oo 1nr J goo_ r o on ooc t t 0...

Страница 279: ...h address OFOOOH the pixel pattern for the character with code 0 is stored in the first 8 bytes the pattern for code 1 in the next 8 bytes and so on The last character pattern for code 07FH is stored...

Страница 280: ...13 18 19 1E 1F Iii 1 8 8lll 0 8ll8 II 8 24 E F 10 11 14 1A 000 8000 000 gos 000 0 0 888 8888 888 8888 00000000 20 15 1B 21 o onsoooo 0 98 0 0 8088 888 8 8 ooog ooo 0 000 000 26 27 16 17 1C 10 22 23 28...

Страница 281: ...HE SCREEN DISPLAY 1111111 r 2A 2B 2C 20 2E 2F 30 51 32 33 34 35 m111m11111 36 37 38 39 3A 38 42 43 44 45 46 47 48 49 4A 4B 4C 40 4E 4F 50 51 52 53 Figure 7 5 The Alternative Character Set 2 of 7 1 1 1...

Страница 282: ...o oaoo oo amm OlJlJ l JOClll 4 LJ JlJLIUOUU 01 JOODOfJD 1 1 00 00 OOLl Jl I ClOCl 1 11 00100 a aa Of l llfJll Jll ll I 4 II 000 80008 5 0 1000 000 ODO 000 000 0 10 000 000 ODO ODO ODO Daa ooo lJOOO OD...

Страница 283: ...0 o n 85 olg t 0 1 S 86 8C 98 El7 818 0 000 0 00 u 8 0 00 00 8D 0 01 1 000 fJIJ 0 oo go 88 08 H 000 ot1 oon 010 8 g 11 0 0 D 0 I 0 D O 0 0 tOO 0 i 5 Bf 0 0 0 SE ogco g Bo o DO 0 0 8 D 00 0 89 ODO 00 i...

Страница 284: ...Jl JI 00 8H DOm10coo r 1uo 1 000 1 J I lr Q l s Do11R u n 10 1 Mrnmoo 10 OIJ 0 OfJ O lJ 0 lJ CE 1 iFc oaoaoao i oaoaoao aoaoaca oaoaoao aoaoao 88888B8i1 oor oootJO um1 nuoo H8 ll O L1 00 0 11 B7 ogllo...

Страница 285: ...no 00 DO 01 ui DF 0 0 0 0 0 0 0 0 8 S 0 000 Fl THE SCREEN DISPLAY OOOlJOODO 00000000 l CJQOOOOO 00000000 00000000 00000000 iilil r E2 1 0008 000 0000 ogoo 0 00 DD F5 E6 E7 ES E9 EA EB EC ED EE EF F 1...

Страница 286: ...THE SCREEN DISPLAY re FD FE FF Figure 7 5 The Alternative Character Sat 7 of 7 7 22...

Страница 287: ...ome character display Screen dimensions 12 inches 295 mm Deflection angle 90 degrees Phosphor P31 Display Scale of green Definition 640 horizontal x 400 vertical Bandwidth 23 MHz Refresh rate 56 2 Hz...

Страница 288: ...I MC6845 CRT Controller MA RA Horizontal sync Cursor r I I 2K Memory I character code I left byte I 2K Memory attribute code right byte I I I I I Character generator Shift register Serial dots Vertica...

Страница 289: ...c C ID 0 r 0 a ID en C0 ID a Vertical sync Vertical drive Intensity Video video cascade amplifier Horizontal sync Horizontal drive 0 Grid bias circuits Flyback transformer Vertical coil I CRT Horizont...

Страница 290: ...l Sync 3 Video 4 Horizontal Sync P2 1 Contrast W 2 Contrast LO 3 Contrast HI P5 1 12V 2 GND 11111111 P1E3 C P2 1 6 1 5 Monochrome Deflection Boarc1 from character adapter card BPS Figure 7 B Monochrom...

Страница 291: ...memory is accompanied by at least one processor WAIT state Alternatively video memory can be accessed by DMA The significance of the attribute byte is set out in Figure 7 9 Function Background bits Wr...

Страница 292: ...decimal port addresses are dedicated to the 6845 for the character display card 3B4 Controller Index Register value output via this port points to one or eighteen 6845 internal registers 3B5 Data Regi...

Страница 293: ...ass than number specified in register DJ 2 Horizontal Sync position defines horizontal sync and scan delays Increasing thia value shifts the display to the left decreasing this value shifts the displa...

Страница 294: ...n character block combined value in bits 5 and B D slow blinking 1 11J cursor display 3 fast blinking DBH Cursor definition combined value in bits 0 3 Last scan Line of cursor in character block OCH F...

Страница 295: ...see section Available Adapters in this Chapter The BIOS sate values for an internal monitor but you cen override these values in your own application CHARACTER CURSOR The character display mode curso...

Страница 296: ...ion This card is capable of driving a color CRT The color CRT of the NCR PERSONAL COMPUTER MODEL 4E has the following hardware characteristics Screen dimensions Digital input signals Display Definitio...

Страница 297: ...1 0 b9s n Address Up to 20 lines no 0 0 I Data 0 II ___ Control signals n 32KB 64KB Address Display latch buffer i 6845 CRT Controller Control circuits Graphics serializer Character Alpha ROM seriali...

Страница 298: ...THE SCREEN DISPLAY 1 I I I I I I I I I I I I I I I I I I o5 l i I L z ir j ID J 7 34 o5 2o o E ow f c I I n Figure 7 13 Color CRT Signals...

Страница 299: ...10 Pl 1 Power 2 Ground VA RGB drive to CRT Pin 2 is Ground Jl 15 To controller D connector pins Pin 1 D connector pin 3 3 4 4 5 5 9 6 8 7 7 8 6 THE SCREEN DISPLAY D P3 o Figure 7 14 Color CRT Deflect...

Страница 300: ...haracter display adapter the 6845 The general concept of video display initialization discussed in The Character Display Controller also applies to initializing the graphic display character both in i...

Страница 301: ...the background color The border color in character mode is a software convention it is not actually displayed on the CRT of the NCR PERSONAL COMPUTER 3 set high intensity for color selected by bits O...

Страница 302: ...at the graphics card interprets the attribute byte as color information for the color CRT The significance of the attribute byte is explained in Figure 7 15 Color Black Red Green Blue Cyan Magenta Bro...

Страница 303: ...Character Display Note Values given in parentheses apply to certain industry standard monitors which can be used in con Junction with suitable adapters see section Available Adapters in this Chapter...

Страница 304: ...r graphics medium resolution supports a 640 x 200 pixel monochrome graphic display The NCR high resolution mode of display not usually supported by other personal computers gives a high quality 640 x...

Страница 305: ...g to whether the blue gun is on or not By activating the monochrome bit in the Mode Control Register Port 3D8H it is possible to create a third color palette Color selection is set out in Figure 7 18...

Страница 306: ...r 1 Cyan 1 0 1 0 or 1 Red 1 1 1 D or 1 White Figure 7 18 Low Resolution Graphics Color Selection Notes Background can be eny one of 16 colors 8 basic colors with intensity bit on or off Foreground col...

Страница 307: ...ster port 3D8H bit 7 up to 4 graphic pages can be addressed The memory map for the full 64 KB video memory is as follows OB8000H OB9F3FH even line scans OB9F40H OB9FFFH not used page 1 OBAOOOH OBBF3FH...

Страница 308: ...by a single bit so that each pixel can be displayed as on or off in 16 KB of video memory The video memory addresses used are the same as those ror low resolution graphics The only difference is that...

Страница 309: ...H not used OA8000H OABF3FH even scans 2 6 10 398 OABF40H OABFFFH not used OACOOOH OAFFFFH odd scans 3 7 11 399 OAFF40H OAFFFFH not used As in low resolution graphics each pixel is represented by two b...

Страница 310: ...as shown in Figure 7 22 Register Value hex Register Value hex 0 69 5 0 1 50 6 64 2 58 7 84 3 DA 8 0 4 SB 9 3 Figure 7 22 Control Registers For High Resolution Graphics Figure 7 23 illustrates Mode Co...

Страница 311: ...status line The status line is initially situated at the foot of the display but when pixel plotting or cursor movement approaches the status line it is transposed to the top of the screen and the fo...

Страница 312: ...lowest location occupied by first seen line of hi res color display Maximum x and y screen co ordinate values for high resolution color Repetition factor for fast screen movement Seen code for c L F...

Страница 313: ...code is in AH AH C ODEZ Key Z for zip CYCLE3 Jump if no zip to be activated ZIPCOUNT ZIPFACT SHORT CYCLE1 AH 47H CYCLE5 AH 51H CYCLE5 AL AH Direction arrow scan codas are in range 47H to 51H MDV ZIPK...

Страница 314: ...ORISET DEC ex CMP CX XMAX JZ HORISET XOR cx cx SHA AL 1 ADC DX O SHA AL 1 see DX o CMP DX YMAX 1 JNAE VERTISET DEC DX CMP DX YMAX bit O set right 1 left 2 down 3 up Shift 4 Lses through Carry Flag adj...

Страница 315: ...moved CMP DX 380 JZ STATMOV1 CMP DX 40 JZ STATMOV2 Jlf SHORT POSSET CMP CURROW 24 JZ STATMOV3 JMP SHORT POSSET CMP CURROW 24 JNZ STATMOV4 POP DX POP CX RET No need to move status line Must move bottom...

Страница 316: ...rent co ords Leave old pixel position as it was before illuminating next one MOV AL PIXLOGIC AND AL 1 Ignore all but LSB JNZ DOTPLOT DOTUNPLOT JMP ILLUMINE RET is from this routine DOTPLOT RET Illumin...

Страница 317: ...urn info elso eveileble in ES BX t OL MDV SI VIDEORAM 400H MDV CX BX MDV AX C X AND CX 0003H INC CX Base peregraph of graphics video memory will be raised by 400H on first pass through loop For offset...

Страница 318: ...horizontal coord DX vertical MDV BX AX As return parameter MOV VIOEOOFFS AX Offset into seen block stored POP CX Now estebl ish which two bits of the AND CX DDD3H INC ex MOV AX 03DDH byte calculated r...

Страница 319: ...or Y co ordinate MDV Cl lRCDL 14 CALL SEBlIGITS POP DX POP ex RET Entry binary number in AX cursor row col in Cl lRROW Cl lRCOL PUSH DX So as not to corrupt Y co ordi nets MOY DX WORD PTR Cl lRCDL CAL...

Страница 320: ...gic Coords SI HOV SI OFFSET LOGITEXT HOV OI OFFSET STATTEXT1 69 HOV CX 7 CLO REP MOV B SI correct following previous MOV B STAT1 1 66 HOV CURCOL O HOV OX WORO PTR 0 IRCOL CALL CURSET HOV BX OFFSET STA...

Страница 321: ...ordinates ss MDV DX VERTIPIX they were erased by nm status line CALL DISPCOORDS build up RET i i ROM BIOS reed from keyboard buffer seen code in AH i i Keyboard reed function MOV AH O INT KBCHINT RET...

Страница 322: ...MDV SI AX XOR AX AX MDV DI AX KIV BL 2 HOV CX 320 CLO REP STOSW ADD SI 40DH MDV ES SI XOR DI DI DEC BL JNZ CLB2 MDV AX BANDPARAG For paragraph addition to address subsequent scan blocks Fill band with...

Страница 323: ...AND AX OEFFFH DEC DL JNZ SHOWB1 RET character Address 2nd seen block in B6DD or ABDO video memory Get paragraph eddr es for B800 block change B to A Copy 16 seen lines video memory to BANDSTORE This...

Страница 324: ...L ILLUMINE PUSH DX Neutralize current cursor point BLUEDN BLUEOFF IXlL2BITS 60 KIV DX 3D9H Graphic controller color selection MDV AL CCI NJMBER Velue 0 7 INC AL Step to next color MDV CCLN IMBER AL St...

Страница 325: ...arameter CL bytes higher if Replace AH need not be zeroed MDV DI OFFSET LOGITEXT PUSH OS POP ES MDV CX 7 CLO REP MOVSB CALL STATLINE CALL ILLUMINE RET Data 11 Ii I ZIPKEY DB 0 Occupied by scan code of...

Страница 326: ...video byte D move only 1 replace Color in 3 LSBs 5 MSBs irrelevant To contain 4 2 bit copies of color ODDO _ 000010108 000010008 000010018 D 000000108 D 000000018 0 00000110B 00000100B 00000101B D ke...

Страница 327: ...pplied to the character and graphics cursor display controller conversion is applied to most of the other registers of the 6845 written via ports 3B4H 3B5H This conversion ensures that display control...

Страница 328: ...C C C...

Страница 329: ...NumLock and CapsLock keys LEDs are extinguished at power up initialization so that unshifted not shifted and cursor movement not digit keys are active Tilting positions the keyboard in one of two poss...

Страница 330: ...e keyboard is 4 75 V 5 25 V the maximum power drain is 150 mA Required signal levels for Clock and Data are minimum 2 4 V for high and maximum 0 7 V for low Data transmission is clocked as illustrated...

Страница 331: ...THE KEYBOARD C C Figure a a Keyboard Common Keys 8 5...

Страница 332: ...Cb I ID C ID a a 0 a ID CT 0 CD a C IJ m 16 m 1 l klRI Fl F2 Fl F4 FS F6 F7 FB F9 FIO Esc I 1 Clrl L I rAll I r 1 I 1 t l...

Страница 333: ...CD I a Cl m er a a il C m cc OI n 1 Ye I Y Fl Fl L I r 1 1 1 1 1 11 11 c 0 ISc oCI Esc I I3 0 1 PgUp lock CUI Fl F4 PgOn 7 8 9 End Hom t Pg Up F5 F6 A Is lo lF le lH IJ lK IL I I I I I i L 5 6 I F7 F...

Страница 334: ...Q I 0 Tl IC C CD 0 c 0 Cl l I CD C 0 m Q Ii CD 3 m re r Fl F2 FJ F4 FS F6 F7 Fa F9 FIO t t i...

Страница 335: ...Q I I Tl IQ C m m 0 a i t m r r 0 m a I Tl m I 1 Ye I Y Fl F2 Esc 1 lllt PgUp 0 1Saoll Lock FJ F A End PgOn 7 8 9 Home t PgUp F5 F6 I 10 f 4 5 6 I Clrl u I F7 FB F9 FIO All L tt s...

Страница 336: ...cc C a m s CJ1 0 a a C 0 m a 1 4 m m t t i a Vir Fl F2 I 1 I I I _IL 11 11 c 0 jScroll 5 Doi PgUp Lock Clrl FJ F4 PgDn 7 8 9 End Horne t PgUp FS F6 A IS ID IF IG IH IJ IK IL l iil I I I I Ii 5 6 I F7...

Страница 337: ...0C I o Tl CD C m a CJ 0 D m D 0 m D rn 0 m m r 0 n 1 re i Fl F2 Oil IPgUpI I f C 0 Sc I Leck FJ H F5 F6 1 I 9 nd IPgDn I 7 e 9 Home f Pg Up 0 IF IG IH IJ K IL IN I I 4 s 6 I F7 Fl F9 FlO tt I...

Страница 338: ...nterval of eight scan cycles CODE GEBBRATION An 8039 or 8049 microprocessor controls generation of key codes for serial output to the main unit see Figure 8 5 Note that the code generated represents a...

Страница 339: ...ode output The keyboard read routine contained in the system ROM is activated by hardware interrupt request 1 CPU interrupt type 9 The priority of this interrupt as set by the initialization firmware...

Страница 340: ...by means of your own software for example if you only want to check for a limited number of codes and ignore the keyboard buffer you will have to write your own keyboard handling routine and set the f...

Страница 341: ...THE KEYBOARD F gure B 6 Keyboard Pos t on Codes 8 l s...

Страница 342: ...key Invert Aux Flagcopy forltest only Aux Flag CCIJ Y true Set clear Aux Flag Send Numlock down Send Numlock up Position Code Key up Code Set bit 7 1 Send Code Normaly End go to new scan Figure B 7 S...

Страница 343: ...e set as shown in Figure 8 8 Figure a a Advanced Keyboard Equipment Selection Possible tilting planes are 5 and 12 degrees An LED is present in the ScrollLock key just like the NumLock and CapsLock LE...

Страница 344: ...activity until another key is pressed Function Keys F11 F30 do not issue codes to the system but take on the following functions internal to the keyboard F11 toggle to enable disable autonomous codes...

Страница 345: ...F21 toggle NumLock repeat non repeat Default is non repeat Autonomous codes are active when the LED in the Alt key is illuminated This Function Key extension can be installed in advanced keyboards whi...

Страница 346: ...0c I l l 0c Tl IC C ID m ia Cl m I n m Cl ID er 0 m Cl en n m I n 0 Cl m m Alternate code translation by system other NCR equipment only gr Code transmitted to system ttt eJ...

Страница 347: ...THE KEYBOARD Figure B 10 Advanced Keyboard Common Keys 8 19...

Страница 348: ...HE KEYBOARD a I r t t Figure B 11 1 of 9 Advanced Keyboard US English 8 20...

Страница 349: ...THE KEYBOARD C rl I t r Figure B 11 2 of 9 Advanced Keyboard UK English 8 21...

Страница 350: ...THE KEYBOARD r it 1 I It t It r i Figure B 11 3 of 9 Advanced Keyboard Germen 8 22...

Страница 351: ...THE KEYBOARD t z J r I_ l Figure 8 11 4 of 9 Advanced Keyboard French 8 23...

Страница 352: ...THE KEYBOARD Ji I 1 I I f t r B U _ i j 1 01 Figure B 11 5 of 9 Advanced Keyboard Italian 8 24...

Страница 353: ...THE KEYBOARD C C 1 1 fl lo I t 1 Figure 8 11 6 of 9 Advanced Keyboard Spanish 8 25...

Страница 354: ...THE KEYBOARD r I C t f Figure B 11 7 of 9 Advanced Keyboard Danish 8 26...

Страница 355: ...THE KEYBOARD u I liJ u al ll l h w Im IO N J I 3 D r ii s It I f Figure 8 11 B of 9 Advanced Keyboard Norwegian 8 27...

Страница 356: ...THE KEYBOARD r It l i t Figure 8 11 9 of 9 Advanced Keyboard Swedish Finnish 8 28...

Страница 357: ...ound effects can take place while other instructions are being processed The timer integrated circuit is described in Chapter 2 The signal from the parallel input output IC can be controlled by OUT 2...

Страница 358: ...is routine in CPU registers as follows DX number of CLK 2 triggers to be counted before OUT 2 is activated Because this process is self repeating see above without software intervention this yields th...

Страница 359: ...llowing code creates the sound of a warning siren when repeated continuously The value in CX sets the count for the duration of silence between units of the same tone SI sets the incremental value for...

Страница 360: ...ir respective notes in musical notation useful Figure 9 1 Note Frequency Note Frequency Hz Hz A 220 F 740 A 233 G 784 8 247 GI 830 C 262 A 880 Cf 277 2 A 930 D 293 6 8 987 8 0 311 6 C 1046 4 E 329 6 C...

Страница 361: ...e dividend quotient in AX ignore remainder MDV AL OBSH initialize timer 2 as follows OUT 43H AL access both high and Low counter bytes counter byte values binary not BCD mode 3 square wave generator P...

Страница 362: ...ull stop results in the note not being played in its full length Instead the end of the note is actually transmitted to the loudspeaker output routine as silence OFFFFH This prevents notes from runnin...

Страница 363: ...ignored The EQUate BEAT sets the metronome beat rate as a multiple of the minimum beat unit A digit at the beginning of a note specifying command results in the note being played for a corresponding...

Страница 364: ...encies READTUNE MDV SI DFFSET TUNE MOV BX OFFSET A2 START at this instruction MOV OCTAVE BX Therefore notes A Gare in this octave until further octave command MOV KEYDISP O No change of key MOV AL BEA...

Страница 365: ...metro min beet Parse string for key command Kn or end if found return to IDMUSIC to Look for next item KEY MDV AL SI INC SI CMP AL K JNE TEMPO MDV AL SI CMP AL 1 JB ENDCHK CMP AL 19 1 JA ENDCHK SI E...

Страница 366: ...mum beat If found return to search for next music item TEMPO CMP AL M JNE TEMP02 MOV AL SI CMP AL 1 I JNE TEMP011 INC METRO INC SI JMP IDMUSIC Jump if no change to metronome beet This char must be or...

Страница 367: ...note Length octave command n or N or b one or more Check for digit specifying Length of note Length digit n METRO LENGTHD CMP AL 11 1 JB OCTVCHK Jump if Length not specified CMP JA SUB l V XOR MUL MOV...

Страница 368: ...ain next octave NOTE There is no range checking Illegal notes are detected in RDNOTE Jump if no octave commend Octave command detected so fat ch next char Jump if octave change only temporary Otherwis...

Страница 369: ...in CL Check that note is within Legel range 1 2AH NOTFLAT NBYKEY MDV ADD NOTECHK CMP JB CMP JNA OUTRANGE MDV NDTECHKD MDV AH KEYDISP AH CL AH 1 ClJTRANGE AH 2AH NOTECHKD AH O CL AH KEYDISP zero unless...

Страница 370: ...itten to COMPTUNE The second word pair expanded from OX is not written if the note is to be audible in its entire nominal Length TOSPK 9 14 PUSH BX PUSH ex BX now needed as XLAT pointer MDV MDV SHL PU...

Страница 371: ...gth Entry Frequency Hz in ex Length in BX HOV DX 12H It JV AX 34DCH DIV ex Reference dividend in DX AX Quotient in AX ignore remainder PUSH AX HOV AL OB6H Initialize Timer 2 as follows OUT TIMER 3 AL...

Страница 372: ...ned off 1 3 4 6 8 9 0BH ODH OFH 1OH 12H 14H 15H 17H 19H 1BH 1CH 1EH 20H 21 H 23H 25H 27H 2BH 2AH Intermediate frequency natural notes OFFFFH Effectively silence 220 233 247 262 277 294 312 330 349 370...

Страница 373: ...THE LOUDSPEAKER DB M M M M and slower DB 1 C D E F G G G G A F c A 36 a DB 1 A F c A 3G a DB G F F F F E E E E D E D C E G D 1 DB G F F F F E E E E D E D 2CS 1 CSEG ENDS END 9 17...

Страница 374: ...C C C...

Страница 375: ...solution as defined in Chapter 7 The display controller is configured as for the external color monitor see Chapter 7 Software switching between the two functions is controlled by a switch board see A...

Страница 376: ...a I r CH I POWER SUPPLY I I 5 1 I I I I I I VJ r odcm D1200S VIDF Q RS 23_2 C RS 232 C I _____ 5V Pe l _ _ _ _ _J Keyboard DS TIL R n Sv A nlo r n 1 1 1 E TX Gra Xl Contr Contr t d 0 0 tl I I I I I I...

Страница 377: ...D PC 4i BUS 0 Cl I m 0 OJ 0 Ci C l 0 Ul m X I H z H l 0 t l rt 0 z r i l l 0 n 0 t l r n r Ci m 0 1 C H n z l r 0 t l n i J x i n t l 7 j v j C i Cl l l A K_ OJ 3 C 0 l C l r i t l 3 0 C H i 0 rt 3 I...

Страница 378: ...7 is high for Videotex RGB input low for composite signal from VLP FBAS is composite signal from VLP 75 Ohm Pin 9 is high for 18 KHz MODEM AND VLP CONNECTION The Videotex adapter is designed to work...

Страница 379: ...ammed at low level to another baud rate see later section Figure 10 4 illustrates pin designations for the modem video connector Figures 10 5 and 10 6 show the use of lines 1 10 by the three types of...

Страница 380: ...1 I I S1 20 I I S2 4 4 j 6 I I 7 I I I I E MC1489 I I D2 3 II I L 6 I I U4 I ___ _j I I 1 I I I Moclcm tautomatic dialling I I I SD 6 1 4 i I l 10 s II I __ 1f I ED sJ 9 ED II I I s E 2 7 E I I l l I...

Страница 381: ...modem activity S2 X Request to Sand GNl X X X Ground SD X Transmit Data ED X Receive Data s X Control Figure 10 6 Modem Signal Control Lines SWITCHES The functioning of the Videotex adapter is depende...

Страница 382: ...R04 4 9 IRQ5 5 8 IRQ6 6 7 IRQ7 XB yes no Phase Lock loop fitter sat for video recorder no yes Phase Lock Loop fitter set for VLP XS 1 5 all others Video memory starts at 70000H 2 6 I OBOOOOH 3 7 I ODO...

Страница 383: ...character set DRCS DCOOO 59 Videotex Controller registers 0 58 DC03A This memory map applies to the stack mode of display this being the mode most conducive to implementation of the CEPT norm other m...

Страница 384: ...ER bit 7 OJ display Select manual bit 7 1 or automatic bit 7 OJ dialling modem Select display horizontal sync bit 7 D 15 KHz Videotex vertical sync 50 Hz bit 7 1 18 KHz Videotax vertical sync 60 Hz Sc...

Страница 385: ...bit can be set when defining attributes for a character Setting this bit has the effect that the character table currently selected will apply to further occurrences of that particular character code...

Страница 386: ...aracters The Videotex Controller contains in its own read only memory the patterns of 512 alphanumeric and graphic characters in four separate tables of 128 characters each see Figures 10 10 10 13 The...

Страница 387: ...p l r 6 g 7 p 1 2 lE I E I e I 1 2 A B Q R a b q 1 3 4 5 6 7 I r r CE u C E I I r r r r u a e 1 0 a a 0 1J 314 5 6 7 l C D E F G s T u V w C d e f g s t u V w 8 9 A B r 0 u A r l l a p e 0 8 9 I H I...

Страница 388: ...I I N s C I I I Ii IS I C I A ICEJG I I ac e1 g _ I _ RY I II r r r t 1 yo 1 I I D u u I I d d b u s 5 6 1 I a 9 A I B C D E F I I G H JS w YA E I 0 u a le 1 a li g J S w y u z le t l i 1 I 1 i J i I...

Страница 389: ...C t 1 Ill ffi r u pl al al A A L 1 1 1 II I I I I en V u CD I 0 I I I L tJ I 0 1 0 1 C I I CD L 6 t u r 11 r i J FJ X t f r 1 M r r 4li f N L L ti N r r i I I a I a1 Q 0 I I fd1 I C 0 1 NIM U l CD I c...

Страница 390: ...VIDE01 EX Figure 10 13 FfJH Character Set Table 4 10 16...

Страница 391: ...racter line More than one such character format is possible even within a single display line The actual format used is encoded in the display information for each defined character Figure 10 14 summa...

Страница 392: ...presented by a 16 bit word the upper bits being in the even byte The format 1 14 Figure 10 14 selected is encoded in four bits in this 16 bit word bits 15 14 and 6 7 Figure 10 15 For most formats the...

Страница 393: ...a color for the next pixel and so on An example for Format 9 is given in Figure 10 17 where the color look up tables for each pixel is denoted by a number 0 3 FORMAT 3 FORMAT 10 The 6 pixel line patte...

Страница 394: ...el line pattern is given twice in each word An example for Mode 6 is given in Figure 10 21 FORMAT 7 FORMAT 14 These formats like 6 and 13 affect alternate pixel lines They also resemble 5 and 12 in th...

Страница 395: ...0 0 00011000 00110000 00100000 0 0 1 0 0 0 0 0 00010000 D O O O 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 Bytes 18 and 19 Fo t code Display character First Pixel Seventh Pixel I 1 0 0 0 0 0 0 0 0 0 1 1...

Страница 396: ...0 0 D 1 2 2 0 0 D O O O O O 1 1 2 2 2 D O O O O O 1 1 1 2 2 2 2 0 0 0 0 1 1 1 1 2 2 2 2 2 0 0 1 1 1 1 1 2 2 2 2 2 2 1 1 1 1 1 1 2 2 2 2 2 3 3 1 1 1 1 1 2 2 2 2 3 3 3 3 1 1 1 1 0 0 1 0 0 0 0 0 D O 1 1...

Страница 397: ...1 0 1 1 0 0 1 0 1 0 1 1 0 0 1 0 1 0100001 1 0100001 1 0100011 1 0100011 1 0 0 1 0 1 1 0 100101 1 0 1 0 0 0 1 1 0 0 1 0 0 0 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0 Foraat code o splay character 100011...

Страница 398: ...1 0 1 1 1 1 0 0 0 1 0 0 1 1 1 1 1 0 1 1 1 1 1 0 010111 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 01000001 1 0 1 1 0 0 0 0 0100001 1 1 0 1 1 1 0 0 0 010001 1 1 1 0 1 1 1 1 0 0 0 1 0 0 1 1 1...

Страница 399: ...0 11001100 1 1 1 1 0 D 1 1 11001100 11110011 First Pixel Color bit 2 I First Pixel Color MSB I I 0 0 1 1 0 0 D D 1 1 D O D D O 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 D D O O 1 1 1 1 1 1 0 0 1 1 1 1 0 0 1...

Страница 400: ...0 fl 11000011 1 1 1 1 0 0 0 0 11000111 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 0 0 0 D 0 1 1 o o o a 1 1 1 1 1 1 D O 0 0 1 1 0 0 0 1 1 1 1 1 1 1 1 0 D D 11001111 1 1 1 1...

Страница 401: ...1100001 1 1 1 1 D 1 0 1 0 1 1 0 0 1 1 1 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 0 0 1 1 1 D 1 0 1 0 First Pixel Color MSB I D 1 0 0 0 0 0 D 01110011 D 1 1 1 1 1 D 0 01001100 D 1 0 0 1 1 1 1 01110011 D 1 0 0 0 0...

Страница 402: ...___ 1 1 I l _J Figure 10 23 Attribute Memory Dynamic Allocation The Videotex Controller achieves this economy by looking for an attribute pointer bit when writing a character if bit 7 of the encoded c...

Страница 403: ...oller registers see below Pis the pointer bit indicating that at least one more attribute follows for the current character set or that this is the last or only attribute zero for that character The L...

Страница 404: ...Figure 10 25 p 1 1 0 L T2 T1 TO L Lock bit TO T2 character table p 1 1 1 0 0 H w Double Haight and or double Width on character p 1 1 1 D 1 0 u Underl i na toggle p 1 1 1 0 1 1 I Invert p 1 1 1 1 0 0...

Страница 405: ...0 1 1 1 0 0 50 of 1 Hz 2 Hz 0 1 1 1 0 0 0 1 1 1 1 0 33 of 1 Hz 2 Hz 0 1 1 1 1 1 Figure 10 25 Blinking Attribute COLOR SELECTION Color Layers Colors are selectable for three display layers In addition...

Страница 406: ...ceal attribute ZOOM effects double height magnification displacement of following Lines CURSOR set on the Line in which cursor is to be displayed more than one cursor is allowed cursor form is set by...

Страница 407: ...s the same colors in half intensity These 32 12 bit items of color information are stored in 96 bytes near the top of the 4 KB RAM area at the disposal of the Videotex Controller see Videotex Memory O...

Страница 408: ...racter or pixel in DRCS 4 bit pixel display as transparent Transparency on the screen layer line color see Color Layers means that input from a composite video signal can be accepted on that layer In...

Страница 409: ...I INVERT 1 1 I I I I B Background F Foreground normal I B Lina I transparentl 1 I I transparent line line I I I I Figure 10 28 Layer transparency line the illuminated CRT area controlled by the 27 li...

Страница 410: ...P input is taking place Otherwise this bit is set controls the signal source for the internal field sync generator 0 text 1 video VLP controls the text composite sync 0 display is non interlaced gener...

Страница 411: ...80 characters par line R5 DISPLAY START Initialization value 1BH This register determines tha vertical start position of text on the CRT In this way the character display can be vertically centred Adj...

Страница 412: ...5 raw Start N 21 n w St rt lf 116 I 115 1 113 I 12 11 lo Stack Mode 6 t vltb 11 Vord addr bl In E1pl1r1t or 80Cb row 3 Prg w1tb 11 Word adlroaaabl A 16 A 15 I A 1 A 13 I A 12 A 11 o Ch rov 6 DRCS addr...

Страница 413: ...VIDEOTEX C 0 0 0 0 0 Q Q Q Q Q II Q Q Q M I I 0 a Q Q Q 0 0 Q oa 0 o C U _ Q Q Q Q CUI iii I Ii o gj j 1 1 g Figure 10 29 Videotex Controller Registers 2 of 2 10 J9...

Страница 414: ...ied in R10 Bit 7 can be used to effect the Underlining attribute R13 ones CUJT Bits 6 7 select one of the 4 color Look up table Locations The remaining bits define the contents of that CLUT entry R14...

Страница 415: ...ay be displayed provided that they form a contiguous block of display lines The visual effect of non contiguous display lines can be achieved by use of the transparency Bit 6 also has an effect on dis...

Страница 416: ...unctions This program like the others in the Videotex package is designed to run under the disk operating system Once loaded it remains in memory as a resident process providing a library of routines...

Страница 417: ...eturn type of modem manual dialling 3 Discontinue modem connection 4 Switch to CEPT standard 5 Switch to PRESTEL standard B Toggle line zoom Double Height in cursor line 7 Switch to display interlace...

Страница 418: ...t 7 at 0DC101H 11 Toggle seen frequency 12 Write e controller register 13 Reed e controller register Entry Return Par atars Entry AX register number OX new register value Entry AX register number DX r...

Страница 419: ...r all characters from current pos to end of Line or until new attrib utes defined or until parallel mode selected Read number of lowest Line in scroll area Read number of uppermost line in scroll area...

Страница 420: ...kground color no in CLUT Entry AX character Return AX D successful D error Return AX status byte 21 Set cursor position Entry 40 41 Display attributes are unaffected AX Line number OX column number Se...

Страница 421: ...dsotsx RAM address to which first byte to be Loaded offset to paragraph ODOOOH ex number of bytes max 4608 Return Bytes at specified Video tax RAM address Entry DS AX address to which first byte is to...

Страница 422: ...to stack mode attributes 82 As function 81 except scroll is downwards 10 48 Entry Return Par tera Entry AX character position 40 Line column or AX OFFFFH current cursor pos DS DX destination addr of...

Страница 423: ...n it is possible to print one or more of Character code memory Attribute Memory DRCS memory The Videotex Controller registers including the scroll map registers The 32 12 bit RGB color values The line...

Страница 424: ...ap for the modem interface is given below Corresponding addresses for the video interface are mapped in the higher area Address hex DC2DO DC201 DC2D2 DC2D3 DC2D4 DC2D5 DC206 DC2D7 USART Register Read...

Страница 425: ...bus for transmission At the same time incoming serial data can be converted into parallel form for transmission to the system PIC features are Baud rate generator generating up to 16 different baud ra...

Страница 426: ...character and stop bit receiving time all bits zero are returned to the Data Holding Register and the Status Register recognizes a framing error PCI Transllitter Data transmission can take place when...

Страница 427: ...ailable for reading by modem control software This hardware interrupt can be extended by means of switch X10 so that an interrupt is also issued whenever the PC has completed serializaton and transmis...

Страница 428: ...11 8 Bits 11 Asynchronous 64X rate SYNCH NUMBER SYNCH TRANS OF SYN CHAR PARENCY CONTROL 0 Double syn 0 Normal 1 Single syn 1 Transparent Note asynchronous mode Baud rate factor applies only if externa...

Страница 429: ...rier FE SYN Detect Overrun PE OLE Detect Ready Detect 0 OSR input 0 DCD input ASYNCH 0 Normal h is high 0 Normal 1 Overrun ASYNCH 1 O R input 1 OCO input 1 Framing error 0 Normal is low is low error 1...

Страница 430: ...has not yet been completely assembled Setting bit 3 forces the TxD line low and holds it low until this bit is reset space after a transmitted character TxD then goes high for at least one bit time b...

Страница 431: ...o DTS DTR RTS and TxD are held high CTS CD DSR and RxD are ignored Receive clock transmit clock provided that Command Register bits O 1 and 5 are set bit 2 is ignored Remote Loop has the following eff...

Страница 432: ...ding Register This bit is zero when the transmitter is enabled by Command Register bit O or when the Status Register is read 3 Assuming parity is enabled this bit set indicates a parity error This bit...

Страница 433: ...t service routine checks for overrun parity and framing errors by reading the Status Register If any of the corresponding bits 3 4 or 5 is set an error condition is recognized otherwise the routine pr...

Страница 434: ...er 0DC201H If modem data is waiting to be read bit 1 set check status for error bits 3 4 5 read character or process error Otherwise check that the Transmit Holding Register is available empty bit O s...

Страница 435: ...he interface procedures for the video video recorder VLP interface are similar to those controlling the modem interfaces The main difference is that the video interface does not make use of interrupt...

Страница 436: ...ude a timeout check on the availabilty of this register When Transmit Holding Register is available write one byte to this register OOC304H Details of the control data protocol with the video unit var...

Страница 437: ...5 kHz H Sync DC000 7 1 vcs Input on Pin 31 DC000 6 1 1MHz on Pin 29 DC000 5 1 FS Output Pin 33 DC000 4 1 Sync Master DC000 2 0 PLL enable DC000 1 1 vcs is used Pin 31 DC000 0 1 Interlace DC003 5 1 WBE...

Страница 438: ...Hz I Sync DC000 7 1 vcs Input on Pin 31 DC000 6 1 1MHz on Pin 29 DC000 5 1 PS Output on Pin 33 DC00004 1 Sync Master DCu00 2 0 PLL Enable DC000 1 1 vcs is used on Pin 31 DC000 0 0 non Interlace DC003...

Страница 439: ...de DClO J 7 DCl00 7 DC003 6 DCl00 7 DOOOO D3FFF last data 1 i luffer cr i ty 0 Output Disable 0 Text Disable Buffer empty Write all Page Memory data DCl00 7 1 Output Enable DC003 6 1 Text Enable Figur...

Страница 440: ...ure 10 36 Wr te V deotex Controller Reg ster DC100 7 1 Buffer empty DC104 7 1 Wait Field Sync Write first Scroll Reg DC104 7 0 Don t wait Field Sync DC100 7 1 Buffer empty DC020 to DC03A Scroll Reg la...

Страница 441: ...lect Clock 3 24 2 12 2 13 2 18 2 21 2 57 5 1 10 1 10 9 10 29 10 33 10 43 10 44 7 4 7 15 7 38 1 9 4 4 4 5 1 5 1 7 1 9 1 12 1 13 1 15 1 28 1 30 2 3 2 4 2 5 2 7 2 28 2 31 2 36 2 37 2 50 2 65 3 15 4 4 5 2...

Страница 442: ...10 37 10 43 1 6 1 16 1 17 1 19 1 27 1 28 1 30 1 31 see 8088 3 11 6 33 6 35 6 42 6 44 6 65 6 67 1 5 1 1 5 2 4 see Chip select 7 64 8 10 8 15 7 23 7 26 7 32 7 35 10 4 10 5 10 10 10 43 10 60 1 7 2 42 2...

Страница 443: ...Gap 3 16 6 13 6 15 6 24 6 29 6 67 Gate 1 30 2 6 2 7 2 8 2 9 6 5 6 6 6 9 6 48 6 49 6 52 6 53 6 54 6 68 9 3 9 5 9 16 GRAFTABL 3 16 7 5 7 15 Head select 6 4 6 5 6 29 6 49 6 51 6 68 High resolution 7 1 7...

Страница 444: ...8 12 8 13 Latency 6 2 6 69 Lock bit 10 11 10 29 10 30 Loopback 4 12 Low resolution 7 15 7 40 7 41 7 42 7 44 Maximum mode 1 7 Medium resolution 7 40 7 44 7 45 10 1 MFM 6 2 6 6 6 12 6 15 6 19 6 20 6 23...

Страница 445: ...10 58 10 59 10 61 10 62 3 9 3 21 7 37 7 41 7 45 7 47 7 56 10 32 10 33 10 34 1 9 1 15 1 28 1 30 1 31 2 1 2 3 2 42 3 4 3 12 4 8 4 9 4 10 4 11 4 12 4 18 4 19 4 22 4 23 10 51 10 52 10 53 10 57 10 58 10 5...

Страница 446: ...13 4 14 4 15 4 22 4 23 5 9 5 13 6 46 10 50 10 51 10 52 10 53 10 56 10 57 10 58 10 59 10 60 10 6 1 1 5 1 6 1 13 2 5 2 64 2 65 2 66 7 23 7 32 2 1 2 7 2 18 2 25 4 31 4 33 6 66 8 10 8 15 8 16 8 17 9 2 9 3...

Страница 447: ...be 2 6 2 7 2 8 2 28 2 31 2 45 2 52 2 53 4 4 4 5 4 24 4 26 4 27 4 28 4 32 9 3 9 5 9 16 Teletype 3 10 7 56 7 57 Timer counter 1 30 2 5 2 29 2 31 3 20 3 21 9 5 Transparency 10 30 10 31 10 34 10 35 10 41...

Страница 448: ...6 53 6 63 3 11 6 2 6 9 6 43 10 11 3 15 7 31 7 41 7 64 8 10 8 10 2 17 7 1 7 28 7 36 7 38 7 44 7 46 1 5 2 2 2 3 1 1 1 7 2 2 2 3 2 11 2 14 2 16 2 19 2 20 2 68 3 1 3 3 3 24 4 18 7 5 8237 1 12 1 21 2 50 2...

Страница 449: ...C C C INDEX 8255 1 21 1 30 2 5 2 42 2 43 2 45 2 48 2 49 8 11 9 1 8259 1 12 1 21 2 5 2 12 2 13 2 26 2 27 8 12 8288 1 15 11 9...

Страница 450: ...c C...

Страница 451: ...ve Flexible Disk Drive 1 2 MB Fixed Disk Drive CRT Monochrome Monochrome Color CRT Power Supply Color Power Supply External Monochrome Monitor External Color Monitor Memory Expansion Board DLC Inhouse...

Страница 452: ...0 0...

Страница 453: ...Early type Main Processor Board C Ill A 1...

Страница 454: ...1 02 13 Cl 11 01 SI J SI u OEN 16 DES 1 81 52 18 S2 92 DIR 4 DATRI 1 C1 sv 16 r ue1 INTAI 14 I INTA I CLKBB 2 s I CLK J1_ NC I AEN 6 IOWC I 4 7K I AEN RO GT osa as JI RD GT1 25 ase 2 as TEST I S2 28 L...

Страница 455: ...04 12 AEN AENI Early type Mein Processor Board 2 of 14 A 3 1 02 2 B1 e 4 C2 4 04 1 A4 2 C2 2 DI 1 04 1 0 FLEX DISK SERIAL 1 F PRINTER 1 F 1 0 llC oC I 04 2 Cl 3 01 4 A4 II RDYTODMA 2 CJ l 04 2 Cl 4 _...

Страница 456: ...I 12 WRfl READ xo s01 011 1 1_ _ A _ 1_ _s__ i I 0 1 1 02 021 9 A l7 I I 0 2 2 103 03t 7 A IB __ I I X 0 3 3 404 Ql l 6 A 19 _ I l sv 1 1 AU l2K I R22 4 7K 27 A1 U118 1 IF U t i I C 98 RGTR XAI 1 1 9...

Страница 457: ...V 16 i 111 411 4 7K L _J l 15 1 2 1 CI ROMAORSL XA9 1 9 XAB 2 1 74LS27 12 74LS27 XIORI I U116 10 U116 sv 16 u101 4 7K L ____ __ CARSLTD 1 2 131 74LSH II INTAI U93 I I 2 BJ RAMAOSEJ 11 6 _64 O OO P ___...

Страница 458: ...5 of 14 A 6 v MA7 9 CID MA7 9 CtO MA6 13 32 32 MA 16 MAS 11 M MA4 UA MAl 12 4 MA MA2 2 2 u I MAI 7 MU E L RAS8 4 I Ne RAse I Ll Nc CASe 15 Cl CA59 15 I Cl La L C2 1 c I C2 La u I Cl _ Cl WE J WE 3 I L...

Страница 459: ...l D AFPi x v x v MU g CID MA g CID 64 MAI 13 3l MA 32 MAS I II MAS II II I A II I MAJ 12 MAJ 12 MA2 I 2 MA1 6 1 MAI 1 1 MAI 1 1 MAI S CID I MAI CID I RAS11 I l NC RASII NC CASI IS Cl CAS1 15 I Cl I Cl...

Страница 460: ...__ BA B Ua Sa A4 Early type Main Processor Board 7 of 14 A 8 x v x v x v MA7 9 CID 84 MA7 9 CID 84 A 9 CID 84 f A8 1l MAI 13 l2 12 12 MAS a MAS 18 18 18 MA4 11 MA 11 8 e I UA MAJ 12 MAJ 12 4 4 4 MA M...

Страница 461: ..._ NC 11 n CAS ll 15 C1 CASll 15 I Cl 7 Lal 4 7K 1 I 1 La I CZ I CZ _ 6 s 7 J 1 MDI La MD2 CJ I Cl WE l WE l I MDJ L L __ M0 4 L o I U50 I U59 MOS MO 1 I 1 rKe I M07 0 A J D 0 A 3 D Early type Main Pro...

Страница 462: ...FF 1 E s I I APHICS CONTROlLER 31 K oo u1i r I GI u t 49 2S ISWl CH 6 ON Ii I I U96 ___ I I Gt 113 APHICS CONTROLLER fil K I n F 7 X I I 18 1 251 Ull2 1 4 7K IS i J 4 7K I 1 FLEXIBLE OISK DRIVE SWITCH...

Страница 463: ...rd 10 of 14 9g 2 R DATU 2 f2 11 no u L ti DATA2 l U DATAJ 2 0ATA4 11 9 n T F1 7 DATA5 15 5 0ATA7 1 7 g I 2 5 9 74LSl4 2 U67 Fl U45 Fl ORVij LS2 1 BUSY 2 F2 18 I i 16 6 1 12 _____ 9 ____ 5 17 l 7US1 I...

Страница 464: ...cs u cs i i cs 1 7 OSR 1 1 6 CTS 198CARR 19 RING 1 t t i l l 1 RXO 2 61 SERL1CS LSI 125 U37 SV l IR 0 _ 4c 1 C4 14 Cl 4 0l NC 12Y h0 1 1 NC NC NC NC sv Early type Main Processor Board 11 of 14 A 12 P1...

Страница 465: ...2 RDI 2 s DACK PSI ll IS PSI TC J 19 WOA CLK 21 WCK 2l ROD 22 ROW JS ROV l4 WP TS 17 IOX 11 61 II lJ FLT RI l2Y Pll 1 L SI YENTiLATOR SPANNUNGSREGLER R2S 47l R26 R27 471 R29 121 R f 12 RJI SIi C7f llh...

Страница 466: ...1 J3 I J4 I JS J6 a22 J1 a 21 J2 I J3 i J4 JS i J6 a 21 Jl a20 1 1 1 J2 I J3 J4j JS I J6 a 20 A12 Early type Main Processor Board 13 of 14 A 14 AU JI a 17 1 0 J2 J3 J4 JS J6 a 17 A15 I114 Al7 J3 I J4...

Страница 467: ...XOI c 2 X07 0 c 31 XAI 4 0l 38 XAl 4 0l 29 XA 2 4 0l 28 XAl 4 Dl 27 u 4 0l 26 ML 4 0l 25 XAI 4 0l 24 XA7 4 0J 23 XU 4 DJ 22 XAt 4 0J 21 XA11 4 DJ 211 XAll 4 0l 19 u 2 01 18 XA1J 4 0l 17 XAl4 4 0l 16 X...

Страница 468: ...L5245 111 74500 VLSI I a Y3 I 11 12 D D Jl9 L4 LS 74LS670 UI I L2 _ ___ _ _ _ _ J 1e D Ul2 U31 f I 25 5 U31 C31 U41 J 74508 u e l lT L _14_oa_ I 7407 Rt2 US7 1DIFLEx I C34 U4 1 IJ 7 504 RPII I C38 JI...

Страница 469: ...7 47 19 42 83 119 1 15 12 20 10 48 14 7 84 120 156 13 28 14 49 14 7 85 121 1 17 14 8 14 50 14 7 86 122 158 15 14 7 51 14 7 87 123 159 16 16 8 52 20 10 BB 124 160 17 16 8 53 14 7 89 125 161 18 16 B 54...

Страница 470: ...1 I 1 ABie 8 fESl AD2 4 us R07CTl AD3 l l A9 7 9 i A10 G 10 31 MN RX AD4 I Al1 11 R07t ml AD I A06 1111 A12 4 1 1 l RP2 AD7 A13 14 sv I 4 A14 4 7K ABB 8 AlS 1 A9 7 4 A16 1 A10 10 A17 17 II A18 I AU 12...

Страница 471: ...gic Diagram HJCLIC 4 77 1 0 7 JPl r I 02 3o I J LAYOUTS AND SCHEMATICS 4 Alternate Mein Processor Board 3 of 14 A 19 r I 7 a 2 3 I U22 OEN 16 I 4 7K I I 1 I L BE J sv DEN 2 6 B PRDL cue 2 RESET 2 9 12...

Страница 472: ...F2 JL_ _ IORB 9 Fl 6 6 tEfflB l U29 I 7 EPfU ISEL a 74502 7 2 II a I 607 5 618 121 1 1 Rni S 2 U51 3 6 18 1121 5 4 5 181121 r 74C l c BD4 516181121 i 4 P BOJ S 6181121 74502 U37 7 PI RAI 1 L re 1 74LS...

Страница 473: ...2 RESET IN 13 XI 13 X2 QJ 24111 1 EPROM AO FE 2000 U7 STROBEl 1 6 AUTO FxDT l 1 9 4 INITl 1 6 J SCLINT _l_ _ _ J 4o JD022 DZ 7_____i t i L _1 _ 1I_ Jt 1 _ _ _ QD A TA 3 J2 10 J6 9 OATA4 J2 9 J6 II L 4...

Страница 474: ...LIC0 SY 1 4 _7 IC 7 r I GATE 0 Th JGATE1 GATE 2 0 1 g 71 6 in U l I S 11 i lffl e t liffl l S t fT R TMTA g_ RPg 1 7 1LS74 q sv 1 a o s Q_ ic co u39 I oure I c R OUT I 13 OUT2 17 I 74508 l J U41 US6 U...

Страница 475: ..._ 1 b lz_ _ _ 74LS32 1 8 LJ 6 L_J 7 I 2 56 4 PROI 3 cs 1 8 DAO e 1 1EM SEL 0 HEH SEL 1 c 6 14 16 17 11 n 14 I W G1 hs Ge nux 2 3 9 17 101 7 I I 1 9 6 L_ J 4 R6 8 330 13 14 cs U17 a 1 5 tA0 6 tAI 7 iA...

Страница 476: ...h 1q 7 07 7 m EPROM CS1 Alternate Mein Processor Board 8 of 14 A 24 27128 A0 Al A2 A3 A4 AS A6 A7 AB A9 A10 All A12 A13 Ul4 l5GM I i nA D1 1 I 15 03 lk 04 OS 17 1A 07 a 6 HIPOL 4 7K 6 HIPO RD 0 1 1 4...

Страница 477: ...R l 27 A1 1 11 l 11 RTS 3 BA2 A 2 RTS 32 13 t __ J2 21 JS 7 41 2 1 cs i SE RIAM L JFNL __Jl 0 f7 4 LS 1 2 i5 l 4 7VIC SY LI14 cs UI fGl SERIAL CS 9 I U34 Ji 8 _ 1 I p L _J OSR I 75154 CTS llll CARRIE...

Страница 478: ...LAYOUTS AND SCHEMATICS 7 RAS 7 AS I 14 TPO SV Rl7 4 71 Logic Diagram Alternate Mein Processor Board 10 of 14 A 26 RA11 AOORESS 0 8...

Страница 479: ...1 RP10 3 ROY Jl 30 4 7K lt i Jl 2S RPl0 R9 FE2188 Q 11 RO 1 e liE IIR DAQIN A 7 IICK 7 C 1 INTJN C c I CLK vco ROO 4 ROIi PS1 4 PS8 TtOUT IIDA t 7 OIOCOUT FRISTP l FLT TRO A RST IRl llf 40 INT WT l c...

Страница 480: ...K 112 U3 8 18 Q e PEQUEST RFSH 19 AOSTl I 8 i1 e co ORO I y nAo 1 3 1 18 2A3 I 17 9 ORO l r s LEi co 2 17 RPtl 1 2 14 ORO 2 1 c 1 1 3 16 6 4 7k II C co ORO 3 oicKe 25 L J F 3 112 13 11 RESET 13 RESET...

Страница 481: ...C78 R18 l 1 F J4 4 71 i Rl JVV 100111 w RESET IN0 12V 12V GND SV SV Ql 3906 SPKR HIPOL SV HIPO SW SV LAYOUTS AND SCHEMATICS 6 6 B SVr CRI C13 47 Fl IN4001 RS lMO R20 SV V f 4 71 12V OSC14 Alternate Ma...

Страница 482: ...iV THERE ARE B EXF t NSION SLOTS IIITH THIS C0NFIGURATION JJ2 JJ9 SV t 1C1 9 10 11 14 34 J6 16 J6 IB J6 i B J6 i2 J6 i 4 IJ N c Jll 1 m 11 t1 Jll 3 fE QHAAEN Jll 5 Jll 11 Jll 13 Jll 15 Jll 17 ffi tiHl...

Страница 483: ...i 1 1 017 0040411 1 t L MONITOR BOARD L ALPHA OISPL CONTR BOARD I I _ l 1 _ _ _ _1 I 017 0040329 MONITOR 017 0040329 f_J 017 0040060 I 11 1 I _j Ii I _ i _ P 51 _J 1 _ _ _ fft 1 i L L J I IJ I 1 I I...

Страница 484: ...J I I r J GRAPHIC ADAPT BOARD I I I I i I 017 0040411 _ fl MONITOR BOARD I i l I 0 017 0040330 I L L i _ _J 1 I M I i L _tj _J i it 1 1 i o i I 1 s 1 KEYBOARD 1 t I I Tt 1 I tt i VOLUME r 41 _ r LJ _...

Страница 485: ...C LAYOUTS AND SCHEMATICS FIX DISK C 3277 I LE J POWER SUPPLY 7 0040331 40332 Wiring Diagram 3 of 3...

Страница 486: ...LAYOUTS AND SCHF MATICS Graphics Controller Board JS J3 J4 I J1 A 54...

Страница 487: ...ller Board 1 of 5 S Cl l eJ 8Af 01 I OJ c 01 101 101 sv 5 0l ll LSI CRf CONIAOt LER 114S MAG MAil AEAO wlfiTr 1 CLK I U6 l ENBL MAI 1 REG SEI 1 MAI LIGHT PEN SIR08E 5 I II l REFRESH l II MA1 1 ACJ S l...

Страница 488: ...1 11 12 1 IMS 211 tt I AJ n 1S MAT n 15 IK IA 11 l Al 11 u MAf u l AS l AS l A6 l AI lAT XAT ss J CT XAII XA7 XAII XA7 MATT MAt7 MAU MA ti aIS MATS MATS l AT MAU a 23 MAfl MATl a 17 MATJ MAU a 24 MAT1...

Страница 489: ...LK ___ n 4 sv ruii I I lt JK I I I L _j MCCB MCC7 2 ct n CL IIEkJN TE 5 OSEO IJJIERNAt au _ LAYOUTS AND SCHEMATICS Graphics Controller Board 3 of 5 1 s o 4 81 4 CI 1 A1 4 81 AT S CI AT s ct 5 111 1 A1...

Страница 490: ...i 4 01 SOR lc l l c _ BA I_ __ SY 1 037 l NC NC NC 1 1K L _J 1 ll_ S IA IVS 5 E l I 1 SZ _1 S El J _ _ _ a S E ll J____ Ill P 1 01 Cl o s o o s a 01 OOTCUC 11 b 9 UV Cll en ru is 11 L_ J 17y ru 1 t ly...

Страница 491: ...raphics Controller Board 6 of 5 u s PAL Al Ill AASELI Ill CAS c 111 WINDOW _ I CCLK Ill 1 01 c Ill NC 111 ATL ltH o Ill s l Ill s a 071 c1 H S l NCJ _J RE Fal l 2 CJ CPUENI JI ClOSEO Pl ESSEY ISAMP O...

Страница 492: ...D INTERNAT CHAR OPEN NORDIC CHAR 70 All MIT HCISSKLEBER FIXIERT FASTENED WITH HOT ADHESIVE LABEL SCHM 017 0040060 F AUFGEKLEBT GLUED 3 ITEM 77 GLUED ON SOLDERSIDE 2 NIGHT BESTUCKT C1 JP1 JP3 P2 NOT MO...

Страница 493: ...2 Cl _ SL ll i 1 tc RGRT 4 D4 Al 2 4 9 NC JL NC NC L_ I c J CUR 4CO m _2 C UR S0R l Al l_ NC l C OISPEN S 7 OISEN L NC NC NC NC NC _ NC J NC 3 A3 Alpha Controller Board 1 of 4 IV v 1124 _ v 112 _ vu l...

Страница 494: ...82 4 B2 VD7 XD7 XD7 VD6 XD6 X06 VOS xos xos V04 X04 xo VDl XOl X03 VD2 X02 X02 V01 XD1 xo vo XO XOI 2 C1 XD8 XD7 Alpha Controller Board 2 of 4 A 42 _83 _ DA T A_ G _AT E I 4 B2 l R r i A2 A3 A4 AS A6...

Страница 495: ...lpha Control lar Board 3 of 4 II 17 15 IJ 1 81 ASC0 ASC7 J AJ 1 C2 c I Cl 1 C4 c H NT a RII 1 2K JP2 0 INlERN t T CHAR N _ z o c 1 1 2 C3 NC vv UNDERLINE XI X2 18 All SV ASCI ASCS ASC4 ASCJ ASC2 ASCI...

Страница 496: ...5 4 8l AJ 4 83 Al B 11 MEMW MEMW 4 8l 4 8l A 31 Al A 28 3 1 B 12 MM NC A2 NC A1 NC A 4 83 NC 2_ 2 1l STATUSSEL i 1 1 NC J 04 1 C4 4 CJ CPIJM EL 2 Dl 4 Bl MEMR 2 81 2 82 4 83 2 02 4 84 E M W 9 a 11 1 s...

Страница 497: ...1 HO SENSE J12 2 B c G N u 9 RA2 C34 S3 I SOPS 47K SI SOPO Jll 3 o oc GNO GND S2 2 RII RESERVED J11 5V 5V J5 7 DOD 0 000 SOPE 22M 47M J i 1 J2 I 3 25V 25V 12V r 12V 12V I 1 IC19 C 12V J2 2 GNO C3T C3...

Страница 498: ...2 1511 W LED 51 CR51 JS 3 INDEX SENSOR GRAY 2 R51 150 MW cs1 CR52 lllllll p JS 4 BROWN 3 FLONT LED JS 5 BLUE 4 FPT SENSOR C32 JS 6 ll lM GND BLACK 5 J13 2 lSOPE JS 7 J13 1 so e DOD VIOLET 6 R54 2 2K J...

Страница 499: ...D SCHEMATICS R111 31111 R121 R112 22K 15K c 147M R114 4 7K R113 R121 18K 22K R11512K R11812K Flexible Disk Drive 3 of BJ 5 R112 c 1 21 J 0 SV FPT LED INDEX LED 2 3 1 CONTROL R12S 1311 1 W R111 w W3 A...

Страница 500: ...Control C102 R106 A118 33K r027K 75K C103r 6N1 R107 K 68K 4 SV Al 22KM w 11 FPT LED c101 Ol47I 122M 1HK A112 22M Flexible Disk Drive 4 of B A 48 C105 33M 25V r I 1 I A2 12Vlt I Al Alli 33 A113 Al A115...

Страница 501: ...3 22M 16V C105 e 8 U101 7 _1_______ 0 __ 9 TA7259 6 R104 10 11M3512P 1 6K S R101 1 SK 11 12 13 14 3 2 4 V 4 u C E03 THS 113A 4 W C E01 THS 1113A R102 121 LED101 1113E LED102 19i13E R103 471 12V C101...

Страница 502: ...0K 3 82K 3 VERSION TABLE U101 MS1728P 4 5 6 8 C102 0156J1 C104 10 947 C106 C105 R111 24K 47K 1NeP M C107 R109 R108 1 47M 47K 47K 13353 OR 133212 1332t5 D3442 R105 0 51K U102 MS51721L 2 3 4 5 6 8 R114...

Страница 503: ...TROL 15532001 xx J12 W1 2 GND I 10 I 3 RD 6 j 4i _ 1 8 I I 6 1 F_M _______ 1 7 5V I INDEX SENSOR 1 1 FRONT LED FAT SENSOR 1 G_N D___ 1 g PCBAVFO OPT 15532010 xx J5 _ oo o____ 3 _ 1 _____________ 1_2_v...

Страница 504: ...D SIDE 1 HEAD COMMON ERASE SHIELD COMMON ERASE SHIELD INUSE HEAD LOAD MOTOR ON DRIVE SELECT 0 DRIVE SELECT 1 DRIVE SELECT 2 DRIVE SELECT 3 DIRECTION IN STEP WRITE GATE A 52 Flexible Disk Drive 8 of 8...

Страница 505: ...Ufl flD a i vu uo LD D D 0 11Yt SCLtCT J l Clll UCTC9 Gl1 t ULteT t o nt sntcr t tant uu r z IIC109 DI D1Ut 110 SU t T JtU we1 1 OAU uu 11Atl 00 w uc eouc lfAD D U s10r o11t sruc z r IUOT t1 u1 l D 10...

Страница 506: ...0 2 a2L D2 O l i T IJ 111K I 010 i _ 0 7 07 lb v I D6 ______ 06 06 IS 6C D J O S 06 L_ o t a 03 03 1J 05 O 12 DC UNSAFE 8 D a 9 1 WFIITE FAULT 3K 13 05 OS I 1 ij L J I L lc l_ 17V 12VA T 511c 6 Ti B...

Страница 507: ...C WRITE DATA E W cjg 6H RIWR o i 1 _ __ 26 31 32 LAYOUTS AND SCHEMATICS ____ OUT ENABLE WRITE FAULT DRIVE SELECT R2 v N 5 v l G ACTIVITY LED 5 R 1 5 w ACTIVITY LED F xed D sk Drive 2 of 2 A 66...

Страница 508: ...D LJ I n eoe s Y ATICA1 CANE lJ Li DEFLECTION BOARD foN JalL _ l_ 1 CJIM ___ 911 Cl I con I IIIIClll NI ron VIDEO I I I Ch I I I L mn IOAlll 11 1 I L_ _ _ J U 1 A 11V t 4 I ao 01 ____ L en c t 11111 C...

Страница 509: ...LAYOUTS AND SCHEMATICS Nonochro e Power Supply N 0 GNO o _ _____________ _ TJ 11 RII At4 RIO 10 D 28 C Jg CSI 12v SV O JA 0 25A C14 5 I HCA t2l A 57 NTC I TI R34 Pt R24 s S SINCR s 6 V 50 9 10 R4B C4...

Страница 510: ...LAYOUTS AND SCH EMATICS Color CRT 8 Ill aa m iccz m o ii I a I 0 D L z i n _ er a r 1 m aa11C1 J A 58...

Страница 511: ...MATICS Colar Pa er Supply 11111 11 e A 59 ff ftJ _ J _ _ J _ _ ____ __ H 1 1 _JL f J I crn i111u J 111 v b r 10on EllDII u ftl l j 4UII t S P tr 1r l A _ V uo jLi t r w 5 L9 0 p D P PO A i Do1J r 1111...

Страница 512: ...48 4y t2 3 5 As 0 13 AT y L l SELENi 4 4 A D AU 1 15 5 3 At 0 1 15 ATC I 1 A D US A Tl 7 1 A D 17 AT7 SHT 5 6 I 23 A SHT s 9 2 RMA11 Ht A F i 15 SHT 4 CA CS CCLK I s e cs2 6 WE SHT 5 LS12 106 MC6845 S...

Страница 513: ...19 12A 8 LSl2510 vcc 7 5 J BOOO I 12A LS125 i 7A l P1 R1 I 12A I 12t 11 I LS125 1J BA LSIJ8 JBO JBF II 13 IOR SHT 5 IOW SHT J 4 6 RESET SHT J 4 6 RESET SHT 6 LSCI e se SHT J 2 6845CS SHT 4 6845CS SHT...

Страница 514: ...LSIM LS 74 CURSOR 1 2 3 L J HSYNC DLY SHT 2 SHT 5 7 4 5 I I VSYNC DLY HSYNC 02 a 7 SHT 2 11 o a T SHT J 4 5 7 CURSOR DLY VSYNC I 13 0 12 SHT2 SHT2 1 o a 1s I DISPEN DLY 0 0 SHT 5 SHT 4 5 HCLK 9 I I2 L...

Страница 515: ...CURSOR DLV SHT 4 SHT2 05 SHT 4 SHT I SHT 4 SOOTS SHT J i SHT J 4 RAJ m RAJ m SHT2 PENDLY 11 SHT 4 VCC SH L Cc C 5_ _ ________ SHT 4 OGEN SITO 1 1 SJ2 I I S86 SHT LSe 12C J1 LS24 RED GREEN I I ul j __...

Страница 516: ...A r WEOil 2 MDJ 640COLOA I _ 6 __ 1 DO SHTJ SHT 3 5 6 P1 A31 c HT J f 5 c HT A SHT 4 HI 4 SHT 5 jl T J SHT 4 SHT 5 SHT 5 SHT 5 SHT 4 SHT 6 SHT 3 SHT4 fi 6845 LSJ74 DO D7 fl 33 D8 MA0 1 l I 12B 1 32 QI...

Страница 517: ...4 16 BD2 6 14 803 8 12 B04 11 9 BD5 13 7 BD6 15 5 B07 17 3 1G 2G y1 y14 LAYOUTS AND SCHEMATICS 90 LS37 CCII 3 D 0 2 CC1 4 D 0 5 CC2 7 D 0 6 CC3 8 D 0 9 CC4 13 D 0 12 ccs 14 D 0 15 CC6 17 D 0 16 CC7 1...

Страница 518: ...86 CAS CC 1 4F LS86 1E SA D 9 Ls0 8 LS84 LS86 1 LS98 3 4 6 2 30 J CAS SF 5 __ LS84 3 4 69 84 NS PERIOO 14MHZ 7MHZ 2 J RAS 01 2A Silt 13 586 4f8 LS125 f l11 12b 11 Si l SA 1e 1 113 LS84 13 12 SA V 5 _...

Страница 519: ...E R 04 04 BB o J 13 05 05 1 1 2716 2732 c 11A 1 14 06 06 l J J 7 19 iJ oae 1 7 e l J B 1 11 07 07 16 J i n A9 07 tt f I 2 A 8 IA 08 0 8 19 5 23 A 8 06 15 2 9 CLR CLKCLR A7 os8 1 S1 L CCLATCH 11 1 p L...

Страница 520: ...1 is 2 WE IE LS84 1 2 CPU MEM SEL t r 1 I 11 3 bcLK o CLR IF LS84 1 1 o GRPH vcc 8 AT LATCH SHTU SHT4 SHT 2 SHT 2 SHT J SHT 2 SHT 2 3 SHT 2 SHTJ IF LS94 d 0 READY P1 A18 MEMr COLOR SEL CO HCLK LCLK VS...

Страница 521: ...HT 3 4 5 6 1F Hl SHT6 H2 12 9 SE SHT 6 LCLK 11 8 SHT 4 12 12A vcc L5244 12 AJ HSYNC OLY 2 2K 03 05 BW2 02 SHT 5 vcc 40 50 SD 57 3 58MHZ 01 SHT4 2N3904 SHT 5 14MHZ 13 A7 33 J2 R6 51 RS HNI r 14MHZ i4 J...

Страница 522: ...LAYOUTS AND SCHEMATICS Meaory Expansion Board UI 5 U10 Ul9 u u u ii N u u I u I u u t u u u N V V u A 70...

Страница 523: ...EM0A I AI I CCA ION 51 1 51 2 51 l 51 4 KB ll2DKBI OH OH ON OH 121KB ll KBI OFF OH ON ON 192KB 1 IKBI ON OFF OH OH 256KB 15121 81 OFF OFF OH ON 201 8 1571KB I OH OH OFF ON l KB ll OKB I OFF ON OFF ON...

Страница 524: ...YOUTS AND SCHEMATICS l Al MA0 MAS MU I CID MA1 MAI 13 II ti II MAJ 4A 1 BJ I At DB0 0B7 81 1 Al _ 1 111 J1 II U47 U48 Memory Expansion Board 2 of 4 A 72 U49 U50 U51 U52 U53 us U45 AF POUi 1 Cl l Ct 4...

Страница 525: ...0 I Al _M A B_ M_A_B 1 1 1c10 MA7 I MAI au 82 L 1 1 A2 W r L 4 DBB DB7 1 82 UL f _ ___ of 1 A2 LAYOUTS AND SCHEMATICS U29 U3G U31 Memory Expansion Board 3 of 4 A 73 U32 U33 U34 U35 U36 AF 1 POUl U27...

Страница 526: ...AND SCHEMATICS MA0 MAB l AI MU I CID 7 I MU 13 MAS MU II MAJ 11 MA7 I 87 RAS4 1 A2 CAS41 080 087 1 Cl Re AS S 4 I A2 5 5 1 x v J1 II U11 U12 Memory Expansion Board 4 of 4 A 74 U13 u1 U15 U16 U17 U18 1...

Страница 527: ...1 0 LAYOUTS AND SCHENATICS DLC Inhouse I F Board LABEL SCHM 017 0042937 B AUFGEKLEBT GLUED 70 72 Label NOTE 2 A 75 NOTEU 75 74 81 78 View A 74 76...

Страница 528: ...C3 1 D JOR 2 04 39 A6 25 31 2 04 AS 26 07 07 37 A 27 C 06 35 Al 28 05 35 Al 29 o 3 At 30 03 Al 33 Al 31 02 DI D 3 Bt ROM 11 2 C4 BIOR JOW MEO 1 04 2 81 I 2 C4 MWR 2 84 PCLKB RI IN INSTAT 810W 12 21 I...

Страница 529: ...TSTART 4MSSTOP 5y Cl 3 4 B Hl IS 18 22 23 28 31 9 l F Rll 1K AOOROE C2 lnF DACK DACK 1 04 DACK 1 C2 BRST 1 Ct HO 0 2 C4 MWR 1 C4 1 D4 1 03 2 A4 2 84 1 C2 BRST ClS lnF I Cl BRST 1l 1 AI TSTOP 12 2 C4...

Страница 530: ...2W 75451 1 12 R19 l1 GRD GRD TOM 13 75450 1 D2 U21 511 CR4 U21 Q 11 4 6 2 TB RIB 5111 CR3 KEY 5 C 5V R16 C14 12V R11 C11 15K 47pF C6 CR1 11l0K 11 1pF 11 1 2 12V R12 J2 T1 11 2 2K R6 7 4 R13 C21 1 7 R...

Страница 531: ...LAYOUTS AND SCHEMATICS v daotax Adapter Board 106 107 os 02 I 104 102 A 79...

Страница 532: ...T 15 RE 14 PMA y TPI 12 CSEU sv C1 S 8 11 14 16 18 27 J0 36 __ _ GRD Cll 4 7 IF 12V l 82 5 82 l 8l l 02 1 D4 l Ol R21 2 7k PUI 1 03 5 82 2 Cl T S 2 C1 1MHz Videotex Adapter Board 1 of 5 A 80 V PT8 V9...

Страница 533: ...2 81 1 C1 1 CI DIAi D1A2 02AJ D3A4 DUS OSA6 D6A7 07AB 2 01 2 81 1 CI D8A9 D9A1d OIGA11 D11Al2 D12A13 013Al4 D1 A15 015A16 PUP3 2 6 PRS2LI 2 CS PBOEI 22 OE BWR 27 WR PMA1 PMA2 9 6264 PMA3 8 BKIIB PMA4...

Страница 534: ..._2__ 1_ 02 c 5 Cl Adapter Board 3 of 5 g 6 WA ITFS HMlkH 01211S l 02 AJ TX 1 A2 1 5 02 5 Al 1 82 2 c J2 14 13 5 Cl l Al 01 A1S 015A16 BO l 7 1 e __ I 1 01 l lllll ll BAl1 2 BAI BAO 12 eo 806 805 eo 80...

Страница 535: ...J AJ AS 1 92 sv 2 DI J o 08A9 D15A16 ETB R25 I DJ J D2 2 7k C12 07 11 tnF 01SA16 NC 1 A15 PMA1S 2 C1 EUR 02 D1JA14 PMA1 RJ2 RM 012A1J PMAIJ 75 D11A12 PMA12 DI A11 PMA11 sv D9AI PMAII R24 0SA9 PMA9 2...

Страница 536: ...c lnF 1 F 21 C21 22lnF 1 CJ lpF J2 L1 4 NC 47 H 02 25 2 C1 R4 3 Ml 12V All 9 A11 1 2K Videotex Adapter Board 5 of 5 A 84 1MHz l Al B A 1 2 _ All l lk SY R4 Ilk CPI IIS1 U13 RXC AD OSR NC PU2 x1e 23 19...

Страница 537: ...LAYOUTS AND SCHEMATICS Vidaotax Switchboard 1 1111 y A 85...

Страница 538: ...1 7f H sv RS R1 2 7K 01 8 Pl 1 BTX Rlf IHK 2 RM RU 75 3 GM Rll 75 4 BM Rll 75 ii YNCI 9 GR0 11 NC IK 1 l 7 6 8 A 86 RI llf RI 47 Videotex Switchboard a 11 II l 11 II ICJ SOSHI ____ IC4 SOSNI ___ SV RI...

Страница 539: ...FQ LLMNG BRIDGES ARE a NTAINED cx INECtoR P2 FROM P2 J TO P2 S FROMPl I TO P2 6 W LL PLUG Wiring Diagram Videotex 1 of 3 l 1 li1 11111 11 111 11 A 87 VOWME CXlUlO AOJUSJ __r BIIIGHlNtSS i j I o _NC _...

Страница 540: ...1 fl l I 111 1 BTX ADAPT BOARD 1 f j 017 0040365 I 1 _ S IT II n I I L _ ___l fu li E u1 J I I 8088 CONTROLLER I I 017 0040439 I i I 1 ii n r I Ji I I I I I ISWITCH BOARD I f l LI GRAPHIC ADAPT BOARD...

Страница 541: ...1 1 lGRD I 7 I O e sc 10 1 I LGRO I z 10 TK IDD 10 I 0 11 LGRQ 11 I I U 1 t w 12 Q LGRO 13 I I HS D u I LGRO IS I o i 1 I 17 LGAO 17 I 1D HS I 11 I u_ I 1 LGRO 11 19 I 20 INDEX Clo I 21 LGRO 01 22 ROY...

Страница 542: ...LAYOUTS AND SCHEMATICS Keyboard CR9 GD a _ R6 r R2 RI 8 1 t 0 f A XI U2 u E J m j i _ _ _ _ __ I C1 T T c CR16 RS C5 Cl c 216 220 217 A 90 U6 U7 c t J Tc 7 4 232 233 221 222 223 s 6 3...

Страница 543: ...U2 nu I nu IHI r GI r rN 1 e I l A W1 ITMI HSI HJS IIJI r I 1 NC I I l _j I 11 L L e _ II II C IL 0 E 1 CDL 14 F IS IS ___________ 1 1 1 IY f t L I s I 11 I I 11 II 11 in M E 11 l _ Cl I CU I I F IIGI...

Страница 544: ...C C...

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