National Semiconductor LMH1983, Руководство пользователя

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1
1
2
2
3
3
4
4
D D
C C
B B
A A
Title
Number Revision Size
A
Date: 11/3/2009 Sheet of
File: C:\Projects\..\POWER SUPPLY.SchDoc Drawn By:
3V3 5V
IN
4
ADJ
6
GND
3
NC
7
SD
8
DAP
9
OUT
5
BYP
1
NC
2
U9
LP3878MR-ADJ
1800pF
C73
C0G/NP0: 0.01uF
C74
D5
LG M670-J2M1-1-0-10-R18-Z
Layout Note: LED
Legend is "5V IN"
D6
LG M670-J2M1-1-0-10-R18-Z
150
R82
Layout Note: LED
Legend is "3.3V"
1
1
2
2
3
3
4
4
8
8
7
7
6
6
5
5
J8
POWER
3V3
LDO_3V3
LDO_3V3
Layout Note: Pin Legend is
"5V IN" (pin 8)
"N/C" (pin 7)
"LDO 3.3V" (pin 6)
"3.3V" (pin 5)
"GND" (pins 1-4)
10uF
C69
10uF
C70
0
R80
1uF
C71
1uF
C72
0.34V
D4
5V
TP30
3V3
1 2
JP17
LDO ENAB
10K
R84
10uF
C68
16V
Power Supply Input and Low-Noise 3.3V LDO Regulator
Layout Note: Unless otherwise noted, label all
ICs, Test Points, Jumpers and Headers per the
component comment. For jumpers and headers,
label pins according to the pin legend noted. All
labels should be present on top and bottom silk
screen (except for ICs).
Note: LDO output voltage
Vout 1V*(1+R_hi/R_lo) = 3.30V
Note: Remove 0R resistor when
applying an external 3.3V power
supply to the 3V3 input.
0.1uF
C106
0.1uF
C108
1uF
C107
1uF
C105
VDD
Layout Note: Distribute caps around the 4 sides of
LMH1983 for decoupling the VDD power supply
plane.
VDD
3V3
10uF
C90
10uF
C91
10uF
C95
10uF
C96
10uF
C97
10uF
C98
TP31
VDD
1uF
C92
1 2
JP18
IDD(U1)
0.01uF
C83
250mA
220 ohm
L6
1uF
C77
1uF
C80
VDD
0.01uF
C86
250mA
220 ohm
L8
1uF
C84
1uF
C85
VDD
0.01uF
C101
250mA
220 ohm
L10
1uF
C99
1uF
C100
VDD
VDD
0.01uF
C79
1uF
C78
250mA
220 ohm
L7
1uF
C75
0.01uF
C89
VDD
1uF
C88
250mA
220 ohm
L9
1uF
C87
VDD
0.01uF
C104
1uF
C103
250mA
220 ohm
L11
1uF
C102
1uF
C81
VDD
0.01uF
C82
250mA
220 ohm
L5
1uF
C76
VDD_PLL1
VDD_PLL2
VDD_PLL34
VDD_CLK4 VDD_CLK3
VDD_CLK2
VDD_CLK1
1uF
C93
10uF
C94
Pin 2 Pin 10
348
R81
1.10k
R83
475
R85
LMH1983 Eval Board - Power
B
Sauerwald
5 5