National Semiconductor LMH1983, Руководство пользователя

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LMH1983 Evaluation Kit Users Guide
Page 12 of 25
PLL1 LOOP FILTER AND VCXO
The LMH1983’s primary phase lock loop, PLL1, provides the following key functions:

Synchronizes the 27 MHz VCXO clock to the reference input

Attenuates (cleans) input jitter

Provides a stable, low-jitter 27 MHz clock for PLLs 2, 3, 4
The external loop filter and 27 MHz VCXO are essential to the performance of PLL1,
which dominates the overall loop response of the LMH1983. The loop response of PLL1
is influenced by the external loop components and can be characterized by its loop
bandwidth and damping factor.
PLL1 is designed for a nominal loop bandwidth of about 3 Hz (min) and damping factor
of 0.70 (min). These were calculated using the approximations below, which assume
nominal I
CP1
= 250uA and DIV_N1 = 1716 for the NTSC input format:
Loop Bandwidth (BW) = R47*I
CP1
*K
VCO
/ DIV_N1
Damping Factor (DF) = 0.5*R47*sqrt[ (C33 || C39)*I
CP1
*K
VCO
/ DIV_N1 ]
Loop Filter
The loop filter components include R47, C39 || C40, and C33. It’s recommended to
avoid use of ceramic capacitors in the loop filter since they exhibit piezoelectric
properties that can cause electrical noise when the board/component is subjected to
vibration or shock. This “shock noise” in the loop filter circuit can result in low-
frequency phase modulation on the VCXO output clock and thus on the downstream PLL
output clocks. Tantalum and film capacitors are used for the loop filter since they do not
exhibit piezo effects.