National Semiconductor LM4985, Руководство пользователя

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I
2
C Signal Generation Board and
Software
(Continued)
Use the WAKE UP TIME section to select one of four
different wake-up times available in both OCL and C-CUPL
modes. The time shown is typical. The actual observed
wake-up time may be different.
Either of the two amplifier output-coupling modes is selected
using the two radio buttons in the
HEADPHONE COUPLING
section. Select the output capacitorless (OCL) operational
mode by clicking the “OCL” button. Select the capacitor-
coupled (C-CUPL) operational mode by clicking the “C-
CUPL” button. Ensure that shorting clips are installed cor-
rectly on jumpers JP8, JP10, and JP11. Refer to Tables 2
and 3.
TABLE 2. OCL Operation
JP8 Short pins 1 and 2 together when the OCL
mode is selected.
JP10 Short this jumper when the OCL is selected
through the I
2
C digital interface.
JP11 Short this jumper when the OCL is selected
through the I
2
C digital interface.
TABLE 3. C-CUPL Operation
JP8 Short pins 2 and 3 together when the
C-CUPL mode is selected.
JP10 Open this jumper when the C-CUPL is
selected through the I
2
C digital interface.
JP11 Open this jumper when the C-CUPL is
selected through the I
2
C digital interface.
The last section of the software’s interface is the ADDRESS
BIT . This bit can be set to 1 or 0. The software will force the
I
2
C interface board to apply a logic low or logic high to the
LM4985’s ADR pin according to the radio button that is
selected. The LM4985 will respond to either of the ad-
dresses selected in the software’s Address Bit control.
PCB Layout Guidelines
This section provides general practical guidelines for PCB
layouts that use various power and ground traces. Designers
should note that these are only "rule-of-thumb" recommen-
dations and the actual results are predicated on the final
layout.
POWER AND GROUND CIRCUITS
Star trace routing techniques (returning individual traces
back to a central point rather than daisy chaining traces
together in a serial manner) can have a major positive im-
pact on low-level signal performance. Star trace routing re-
fers to using individual traces that radiate from a signal point
to feed power and ground to each circuit or even device. This
technique may require greater design time, but should not
increase the final price of the board.
AVOIDING TYPICAL DESIGN/LAYOUT PROBLEMS
Avoid ground loops or running digital and analog traces
parallel to each other (side-by-side) on the same PCB layer.
When traces must cross over each other, do so at 90 de-
grees. Running digital and analog traces at 90 degrees to
each other from the top to the bottom side as much as
possible will minimize capacitive noise coupling and
crosstalk.
Bill of Materials
Designator Description Package Value * Notes
C1 Capacitor C3216-1206 (Surface Mount) 0.47 10V, Tantalum
C2 Capacitor C3216-1206 (Surface Mount) 4.7 50V, Ceramic
C3 Capacitor C3216-1206 (Surface Mount) 0.47 10V, Tantalum
C4 Capacitor C3216-1206 (Surface Mount) 1 50V, Ceramic
C5 Polarized Capacitor TC7343-2917 (Surface Mount) 100 10V, Tantalum
C6 Polarized Capacitor TC7343-2917 (Surface Mount) 100 10V, Tantalum
C7 Capacitor C3216-1206 (Surface Mount) 0.1 50V, Ceramic
J1 3–Conductor Headphone Jack Stereo Headphone Jack (3.5MM)
* Capacitor values in µF
AN-1452
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