National Semiconductor HPC167064, Техническое описание

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30 MHz
AC Electrical Characteristics
(Continued)
(See Notes 1 and 4 and
Figures 1 thru 5 ). V
CC
e
5V
g
10%, T
A
e
0 § C to
a
70 § C for HPC467064. (Continued)
Symbol and Formula Parameter Min Max Units Notes
t
ARR
e
(/4
t
C
b
5 ALE Falling Edge to RD Falling Edge 12 ns
t
ACC
e
t
C
a
WS
b
32 Data Input Valid after Address Output Valid 100 ns
t
RD
e
(/2
t
C
a
WS
b
39 Data Input Valid after RD Falling Edge 60 ns
t
RW
e
(/2
t
C
a
WS
b
14 RD Pulse Width 85 ns
t
DR
e
*/4
t
C
b
15 Hold of Data Input Valid after RD Rising Edge 0 35 ns
t
RDA
e
t
C
b
15 Bus Enable after RD Rising Edge 51 ns
t
ARW
e
(/2
t
C
b
5 ALE Falling Edge to WR Falling Edge 28 ns
t
WW
e
*/4
t
C
a
WS
b
15 WR Pulse Width 101 ns
t
V
e
(/2
t
C
a
WS
b
5 Data Output Valid before WR Rising Edge 94 ns
t
HW
e
(/4
t
C
b
10 Hold of Data Valid after WR Rising Edge 7 ns
t
DAR
e
(/4
t
C
a
WS
b
50 Falling Edge of ALE to Falling Edge of RDY 33 ns
t
RWR
e
t
C
RDY Pulse Width 66 ns
Read
Cycles
Write
Cycles
Ready
Input
** This maximum frequency is attainable provided that this external baud clock has a duty cycle such that the high period includes two (2) falling edges of the CK2
clock.
Note: C
L
e
40 pF.
Note 1: These AC Characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO with rise and fall
times (t
CKIR
and t
CKIL
) on CKI input less than 2.5 ns.
Note 2: Do not design with this parameter unless CKI is driven with an active signal. When using a passive crystal circuit, its stability is not guaranteed if either CKI
or CKO is connected to any external logic other than the passive components of the crystal circuit.
Note 3: t
HAE
is spec’d for case with HLD falling edge occurring at the latest time can be accepted during the present CPU cycle being executed. If HLD falling edge
occurs later, t
HAE
may be as long as (3t
C
a
4 WS
a
72t
C
a
100) depending on the following CPU instruction cycles, its wait states and ready input.
Note 4: WS
e
t
WAIT
c
(number of pre-programmed wait states). Minimum and maximum values are calculated at maximum operating frequency, t
c
e
30.00 MHz,
with one wait state programmed.
Note 5:
Due to emulation restrictionsÐactual limits will be better.
Note 6: Due to tester limitationsÐactual limits will be better.
CKI Input Signal Characteristics
Rise/Fall Time
TL/DD/11046 – 2
Duty Cycle
TL/DD/11046 – 3
FIGURE 1. CKI Input Signal
6