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Shared Memory Support

(Continued)

TL/DD/11046 – 36

FIGURE 28. Shared Memory Application (HPC167064 Interface to Series 32000 System)

Design Considerations

TABLE III. Memory Map of HPC167064 Emulating an HPC16064

FFFF:FFF0

Interrupt Vectors

FFEF:FFD0

JSRP Vectors

FFCF:FFCE

On-Chip ROM

User Memory

C001:C000

(

BFFF:BFFE

External Expansion

Memory

0301:0300

(

02FF:02FE

On-Chip RAM

User RAM

01C1:01C0

(

0195:0194

WATCHDOG Register

WATCHDOG Logic

0192

T0CON Register

0191:0190

TMMODE Register

018F:018

DIVBY Register

018D:018C

T3 Timer

018B:018A

R3 Register

Timer Block T0:T3

0189:0188

T2 Timer

0187:0186

R2 Register

0185:0184

I2CR Register/ R1

0183:0182

I3CR Register/ T1

0181:0180

I4CR Register

015E:015F

EICR

015C

EICON

0153:0152

Port P Register

0151:0150

PWMODE Register

014F:014E

R7 Register

014D:014C

T7 Timer

014B:014A

R6 Register

Timer Block T4:T7

0149:0148

T6 Timer

0147:0146

R5 Register

0145:0144

T5 Timer

0143:0142

R4 Register

0141:0140

T4 Timer

0128

ENUR Register

0126

TBUF Register

0124

RBUF Register

UART

0122

ENUI Register

0120

ENU Register

0104

Port D Input Register

00F5:00F4

BFUN Register

Ports A & B

00F3:00F2

DIR B Register

Control

00F1:00F0

DIR A Register/IBUF

00E6

UPIC Register

UPI Control

00E3:00E2

Port B

Ports A & B

00E1:00E0

Port A/OBUF

00DE

Reserved

00DD:00DC

HALT Enable Register

Port Control

00D8

Port I Input Register

& Interrupt

00D6

SIO Register

Control

00D4

IRCD Register

Registers

00D2

IRPD Register

00D0

ENIR Register

00CF:00CE

X Register

00CD:00CC

B Register

00CB:00CA

K Register

00C9:00C8

A Register

HPC Core

00C7:00C6

PC Register

Registers

00C5:00C4

SP Register

00C3:00C2

Reserved

00C0

PSW Register

00BF:00BE

On-Chip

RAM

User RAM

0001:0000

Содержание HPC167064

Страница 1: ... of exter nal memory enables the HPC to be used in powerful appli cations typically performed by microprocessors and expen sive peripheral chips The microCMOS process results in very low current drain and enables the user to select the optimum speed power product for his system The IDLE and HALT modes provide further current savings The HPC167064 is available only in 68 pin LDCC package Features Y...

Страница 2: ... Logic High 0 7 VCC V VIL2 Logic Low 0 2 VCC V ILI1 Input Leakage Current VIN e 0 and VIN e VCC Note 4 g2 mA ILI2 Input Leakage Current RDY HLD EXUI VIN e 0 b3 b50 mA ILI3 Input Leakage Current B12 RESET e 0 VIN e VCC 0 5 7 mA ILI4 Input Leakage Current EXM VIN e 0 and VIN e VCC Note 4 g10 mA CI Input Capacitance Note 2 10 pF CIO I O Capacitance Note 2 20 pF OUTPUT VOLTAGE LEVELS VOH1 Logic High C...

Страница 3: ...D Falling Edge to Output Data Valid 0 60 ns tOD Rising Edge of URD to Output Data Invalid 5 45 ns Note 6 tDRDY RDRDY Delay from Rising Edge of URD 70 ns tWDW UWR Pulse Width 40 ns tUDS Input Data Valid before Rising Edge of UWR 10 ns tUDH HPC467064 Input Data Hold after Rising Edge of UWR 20 ns tUDH HPC167064 25 ns tA WRRDY Delay from Rising Edge of UWR 70 ns Clocks Timers Microwire Plus External ...

Страница 4: ...ing Edge 18 ns tVP e 4 tC b 5 Hold of Address Valid after ALE Falling Edge 20 ns tARR e 4 tC b 5 ALE Falling Edge to RD Falling Edge 20 ns tACC e tC a WS b 55 Data Input Valid after Address Output Valid 145 ns tRD e 2 tC a WS b 65 Data Input Valid after RD Falling Edge 85 ns tRW e 2 tC a WS b 10 RD Pulse Width 140 ns tDR e 4 tC b 15 Hold of Data Input Valid after RD Rising Edge 0 60 ns tRDA e tC b...

Страница 5: ...tC a 85 HLDA Falling Edge after HLD Falling Edge 151 ns Note 3 tHAD e 4 tC a 85 HLDA Rising Edge after HLD Rising Edge 135 ns tBF e 2 tC a 66 Bus Float after HLDA Falling Edge 99 ns Note 5 tBE e 2 tC a 66 Bus Enable after HLDA Rising Edge 99 ns Note 5 tUAS Address Setup Time to Falling Edge of URD 10 ns tUAH Address Hold Time from Rising Edge of URD 10 ns tRPW URD Pulse Width 100 ns tOE URD Fallin...

Страница 6: ...o 2 falling edges of the CK2 clock Note CL e 40 pF Note 1 These AC Characteristics are guaranteed with external clock drive on CKI having 50 duty cycle and with less than 15 pF load on CKO with rise and fall times tCKIR and tCKIL on CKI input less than 2 5 ns Note 2 Do not design with this parameter unless CKI is driven with an active signal When using a passive crystal circuit its stability is no...

Страница 7: ...s are driven at VIH for logic 1 and VIL for a logic 0 Output timing measurements are made at VCC 2 for both logic 1 and logic 0 FIGURE 2 Input and Output for AC Tests Timing Waveforms TL DD 11046 5 FIGURE 3 CK1 CK2 ALE Timing Diagram TL DD 11046 6 FIGURE 4 Write Cycle 7 ...

Страница 8: ...Timing Waveforms Continued TL DD 11046 7 FIGURE 5 Read Cycle TL DD 11046 8 FIGURE 6 Ready Mode Timing TL DD 11046 9 FIGURE 7 Hold Mode Timing 8 ...

Страница 9: ...Timing Waveforms Continued TL DD 11046 10 FIGURE 8 MICROWIRE Setup Hold Timing TL DD 11046 11 FIGURE 9 UPI Read Timing TL DD 11046 12 FIGURE 10 UPI Write Timing 9 ...

Страница 10: ...he HPC16064 and HPC16083 except as described here The value of EXM is latched on the rising edge of RESET Thus the user may not switch from ROMed to ROMless operation or vice versa without another RESET pulse The security logic can be used to control access to the on chip EPROM This feature is unique to the HPC167064 There is no corresponding mode of opera tion on the HPC16064 or the HPC16083 Spec...

Страница 11: ...000 Angstroms Ð It should be noted that sunlight and certain types of fluores cent lamps have wavelengths in the 3000Ð 4000Ð range After programming opaque labels should be placed over the HPC167064 s window to prevent unintentional erasure Covering the window will also prevent temporary functional failure due to the generation of photo currents The recommended erasure procedure for the HPC167064 ...

Страница 12: ...ART Data Input I7 Port D is an 8 bit input port that can be used as general purpose digital inputs Port P is a 4 bit output port that can be used as general purpose data or selected to be controlled by timers 4 through 7 in order to generate frequency duty cycle and pulse width modulated outputs POWER SUPPLY PINS VCC1 and VCC2 Positive Power Supply GND Ground for On Chip Logic DGND Ground for Outp...

Страница 13: ...rogrammed as inputs or outputs Port pins se lected as inputs are placed in a TRI STATE mode by reset ting corresponding bits in the direction register A write operation to a port pin configured as an input causes the value to be written into the data register a read opera tion returns the value of the pin Writing to port pins config ured as outputs causes the pins to have the same value reading th...

Страница 14: ...orts A B Continued TL DD 11046 20 FIGURE 12 Structure of Port B Pins B0 B1 B2 B5 B6 and B7 Typical Pins TL DD 11046 21 FIGURE 13 Structure of Port B Pins B3 B4 B8 B9 B13 and B14 Timer Synchronous Pins 14 ...

Страница 15: ... PSW register does two thingsÐaddresses are limited to the on chip EPROM range and on chip RAM and Register range and the illegal address detection feature of the WATCH DOG logic is engaged A logic 1 in the EA bit enables accesses to be made anywhere within the 64 kbytes ad dress range and the illegal address detection feature of the WATCHDOG logic is disabled All HPC devices can be used with exte...

Страница 16: ...one wait state With 0 wait states internal ROM accesses are limited to 3 fC max The HPC167064 provides four software selectable Wait States that allow access to slower memories The Wait States are selected by the state of two bits in the PSW register Addi tionally the RDY input may be used to extend the instruc tion cycle allowing the user to interface with slow memories and peripherals TL DD 1104...

Страница 17: ...HPC167064 Interrupts Continued TL DD 11046 24 FIGURE 16 8 Bit External Memory TL DD 11046 25 FIGURE 17 16 Bit External Memory 17 ...

Страница 18: ...riate bit to be set There is no indi cation of the order in which the interrupts have been re ceived The bits are set independently of the fact that the interrupts may be disabled IRPD is a Read Write register The bits corresponding to the maskable external interrupts are normally cleared by the HPC167064 after servicing the interrupts For the interrupts from the on board peripherals the user has ...

Страница 19: ...TL DD 11046 26 FIGURE 18 Block Diagram of Interrupt Logic 19 ...

Страница 20: ...e clock rates The clock input to these two timers may be selected from the following two sources an external pin or derived internally by TL DD 11046 27 FIGURE 19 Timers T0 T1 and T8 with Four Input Capture Registers dividing the clock input Timer T2 has additional capability of being clocked by the timer T3 underflow This allows the user to cascade timers T3 and T2 into a 32 bit timer coun ter Th...

Страница 21: ...nfinite loops and illegal addresses Should the WATCHDOG register not be written to before Timer T0 overflows twice or more often than once every 4096 counts an infinite loop condition is assumed to have oc curred An illegal condition also occurs when the processor generates an illegal address when in the Single Chip modes Any illegal condition forces the WATCHDOG Out put WO pin low The WO pin is a...

Страница 22: ... application Information is visually presented to the operator by means of a LCD display controlled by the COP472 display driver The data to be displayed is sent serially to the COP472 over the MICROWIRE PLUS link Data such as accumulated mileage could be stored and re trieved from the EEPROM COP494 The slave HPC167064 could be used as a fuel injection processor and generate timing signals require...

Страница 23: ... to 128 kHz in binary steps or T3 underflow By selecting a 9 83 MHz crystal all standard baud rates from 75 baud to 38 4 kBaud can be generated The external baud clock source comes from the CKX pin The Transmitter and Receiver can be run at different rates by selecting one to operate from the internal clock and the other from an external source The HPC167064 UART supports two data formats The firs...

Страница 24: ...l bit The HLDA output is multiplexed onto Port B The host uses DMA to interface with the HPC167064 The host initiates a data transfer by activating the HLD input of the HPC167064 In response the HPC167064 places its system bus in a TRI STATE Mode freeing it for use by the host The host waits for the acknowledge signal HLDA from the HPC167064 indicating that the sytem bus is free On receiving the a...

Страница 25: ...r 0151 0150 PWMODE Register 014F 014E R7 Register 014D 014C T7 Timer 014B 014A R6 Register Timer Block T4 T7 0149 0148 T6 Timer 0147 0146 R5 Register 0145 0144 T5 Timer 0143 0142 R4 Register 0141 0140 T4 Timer 0128 ENUR Register 0126 TBUF Register 0124 RBUF Register UART 0122 ENUI Register 0120 ENU Register 0104 Port D Input Register 00F5 00F4 BFUN Register Ports A B 00F3 00F2 DIR B Register Contr...

Страница 26: ...7 Register 014D 014C T7 Timer 014B 014A R6 Register 0149 0148 T6 Timer 0147 0146 R5 Register 0145 0144 T5 Timer 0143 0142 R4 Register 0141 0140 T4 Timer 0128 ENUR Register 0126 TBUF Register 0124 RBUF Register UART 0122 ENUI Register 0120 ENU Register 0104 Port D Input Register 00F5 00F4 BFUN Register Ports A B 00F3 00F2 DIR B Register Control 00F1 00F0 DIR A Register IBUF 00E6 UPIC Register UPI C...

Страница 27: ...p these capacitances but it s more effective to distribute them among the ICs If the design has a fair amount of synchronous logic with outputs that tend to switch simultaneously additional de coupling might be advisable Octal flip flop and buffers in bus oriented circuits might also require more decoupling Note that wire wrapped circuits can require more decou pling than ground plane or multilaye...

Страница 28: ...dressed by the X register This mode automatically increments or decrements the X register by 1 for bytes and by 2 for words Register Indirect Auto Increment and Decrement with Conditional Skip The operand is the memory addressed by the B register This mode automatically increments or decrements the B register by 1 for bytes and by 2 for words The B register is then compared with the K register A s...

Страница 29: ...A 11 8 wA 7 4 ÝA 3 0 RRC A Rotate A right thru C CxA15 x xA0xC RLC A Rotate A left thru C CwA15 w wA0wC SHR A Shift A right 0xA15x xA0xC SHL A Shift A left CwA15w wA0w0 SC Set C 1xC RC Reset C 0xC IFC IF C Do next if C e 1 IFNC IF not C Do next if C e 0 TRANSFER OF CONTROL INSTRUCTIONS JSRP Jump subroutine from table PCxW SP SPa2xSP W tableÝ xPC JSR Jump subroutine relative PCxW SP SPa2xSP PCaÝxPC...

Страница 30: ...y bit of memory I O or registers can be set reset or tested by the single byte bit instructions The bits can be addressed directly or indirectly Since all registers and I O are mapped into the memory it is very easy to manipulate specific bits to do efficient control DECIMAL ADD AND SUBTRACT This instruction is needed to interface with the decimal user world It can handle both 16 bit words and 8 b...

Страница 31: ...bility of remotely accessing the development system at a customer site INFORMATION SYSTEM The Dial A Helper system provides access to an automated information storage and retrieval system that may be ac cessed over standard dial up telephone lines 24 hours a day The system capabilities include a MESSAGE SECTION electronic mail for communications to and from the Micro controller Applications Group ...

Страница 32: ...be available TL DD 11046 39 Examples HPC467064 EL20Ð16k EPROM Commercial temperature 0 C to a70 C LDCC HPC167064 EL20Ð16k EPROM Military temperature b55 C to a125 C LDCC to be used for automotive temperature range also Socket Selection Suggested sockets and extractor tool Socket Ý Amp PLCC Ý821574 1 6141749 YAMAICHI 1C51 0684 390 1C120 0684 204 ENPLAS PLCC 68 1 27 02 Extractors Tool Ý Amp 821566 1...

Страница 33: ...33 ...

Страница 34: ...roperly used in accordance support device or system or to affect its safety or with instructions for use provided in the labeling can effectiveness be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd Japan Ltd 1111 West Bardin Road Fax a49 0 180 530 85 86 13...

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