National Semiconductor DAC121C085, Руководство пользователя

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4.0 Functional Description
4.1 Jumper Settings
Table 1 describes the function of the various
jumpers on the DAC121C08XEB evaluation
board. The evaluation board schematic is shown
in
Figure 12 .
Jumper
Pins 1 & 2 Pins 2 & 3
JP4 V
OUT
Load Select (See Below)
JP5
I
2
C Address Select (See Below)
JP6 Enable V
REF
supply to the DAC.
JP7
Use external
V
REF
from J2.
Set V
REF
= V
A
JP8 Enable V
A
supply to the DAC.
JP9
Use V
A
from the
WV4 board
Use external V
A
from J2.
JP10
Use 3.3V supply
from the WV4
board
Use external
3.3V supply from
TP6.
Jumper JP4 (V
OUT
Load Select)
Left side
pins near
“C”
Connect a 200pF load capacitance
from V
OUT
to GND
Right side
pins near
“R”
Connect a 2k Ω load resistance from
V
OUT
to GND
Address
Jumper JP5 (I
2
C Address Select)
0x0C No jumpers
0x0D Short pins 2 & 3.
0x0E Short pins 1 & 2.
0x08 Short pins 6 & 7.
0x09 Short pins 2 & 3 and pins 6 & 7.
0x0A Short pins 1 & 2 and pins 6 & 7.
0x4C Short pins 5 & 6.
0x4D Short pins 2 & 3 and pins 5 & 6.
0x4E Short pins 1 & 2 and pins 5 & 6.
Table 1: Jumper Configurations
4.2 I
2
C Interface
The DAC supports all three I
2
C speeds, including
Hs-Mode (3.4MHz). In Hs-Mode the maximum
DAC conversion rate is 188.9kHz. The board is
designed with 1k
Ω I
2
C pull-up resistors on both
the SDA and SCL lines (R6 & R7). Also, series
resistors for SCL and SDA are designed into the
board (R8 & R9). The board is shipped with 51
Ω
series resistors which can be increased to
interface to a noisy I
2
C bus.
In Computer Mode , the I
2
C interface is driven by
the WaveVision4 board. The WaveVision4
software allows the user to drive the DAC121C085
with various digitized signals. Refer to
Section 5.0
“Software Operation and Settings” for further
information.
In Stand-Alone Mode , the I
2
C interface must be
driven by an external device. See section 1.4.5 of
the DAC121C081/DAC121C085 datasheet for a
typical write sequence timing diagram.
The maximum digital input level of the I
2
C
interface depends on the analog supply voltage
(V
A
). The interface operates at normal CMOS
logic levels. See the Electrical Characteristics
section of the datasheet for further details.
The SDA signal is accessible by connecting to
pin 2 of the WV4 connector (J3). The SCL signal
is accessible by connecting to pin 6 of J3.
Please refer to section 1.4 of the datasheet for a
detailed description of the I
2
C interface. Refer to
the Philips I2C Specification for further details.
4.3 DAC Reference Circuitry
The reference voltage for the DAC121C085 is
selected by JP7. (See
Table 1 for details.) The
reference can either be selected as the V
A
supply
or an externally supplied voltage (J2). The analog
output range of the DAC121C085 can be scaled
by adjusting the reference voltage (V
REF
). The
lower the V
REF
, the smaller the output range. V
REF
can be set anywhere from 1.0V to V
A
. V
A
is
independent of V
REF
and can be set anywhere
from +2.7V to +5.5V. In any case, V
REF
has little
to no PSRR and must be as clean as possible to
reduce noise feedthrough on V
OUT
.