National Semiconductor CLINK3V28BT-85, Руководство пользователя

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Channel Link Evaluation Kit User Manual
National Semiconductor Corporation
Interface Products
LIT# CLINK3V28BT-85-UM
Rev 2.1
Date: 10/12/2005
Page 6 of 28
Channel Link Transmitter Board Description:
J1 (60 position) accepts 28 bit LVTTL/LVCMOS data, clock and also the PD* control
signal.
The Channel Link Transmitter board is powered externally. For the transmitter to be
operational, the Power Down pin must be set HIGH with a jumper.
The 3M MDR connector (J2) provides the interface for LVDS signals for the
Receiver board.
Vcc and Gnd MUST be
applied externally here
1 2
GND TXIN0
GND TXIN1
GND TXIN2
GND TXIN3
GND TXIN4
GND TXIN5
GND TXIN6
GND
TXIN7
GND TXIN8
GND TXIN9
GND TXIN10
GND
TXIN11
GND TXIN12
GND TXIN13
GND
TXIN14
GND TXIN15
GND TXIN16
GND TXIN17
GND
TXIN18
GND TXIN19
GND TXIN20
GND TXIN21
GND
TXIN22
GND TXIN23
GND TXIN24
GND
TXIN25
GND TXIN26
GND TXIN27
GND TXCLKIN
GND GND
59 60
J1
/PD
J2
Pin 26
Pin 14
Pin 1
Pin 13
NC OUT0-
GND OUT0+
NC NC
OUT1- GND
OUT1+ NC
OUT2- GND
OUT2+ NC
NC NC
NC CLK-
GND CLK+
NC NC
OUT3- GND
OUT3+ NC
TxOUT LVDS signals
3M MDR connector
60-pin IDC Connector
Note: JP1 is not used