National Semiconductor CLINK3V28BT-85, Руководство пользователя

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Channel Link Evaluation Kit User Manual
National Semiconductor Corporation
Interface Products
LIT# CLINK3V28BT-85-UM
Rev 2.1
Date: 10/12/2005
Page 11 of 28
Rx Channel Link Receiver Board:
J1 (60 position) provides access to the 28 bit LVTTL/LVCMOS, clock outputs.
The Channel Link Receiver board is powered from the pads show below. For the
receiver to be operational, the Power Down pin must be set HIGH with the jumper.
The 3M MDR connector (J2) provides the interface for LVDS signals for the
Receiver board.
Vcc and Gnd MUST be
applied externally here
RxIN LVDS signals
3M MDR26-7 connector
/PD
60 59
RXOUT27 GND
RXOUT26 GND
RXOUT25 GND
RXOUT24 GND
RXOUT23 GND
RXOUT22 GND
RXOUT21 GND
RXOUT20 GND
RXOUT19 GND
RXOUT18 GND
RXOUT17
GND
RXOUT16 GND
RXOUT15 GND
RXOUT14 GND
RXOUT13 GND
RXOUT12 GND
RXOUT11 GND
RXOUT10 GND
RXOUT9 GND
RXOUT8 GND
RXOUT7 GND
RXOUT6
GND
RXOUT5 GND
RXOUT4 GND
RXOUT3 GND
RXOUT2 GND
RXOUT1 GND
RXOUT0 GND
RXCLKOUT
GND
GND GND
2 1
J1
J2
Pin 1
Pin 13
Pin 26
Pin 14
NC IN0-
GND IN0+
NC NC
IN1- GND
IN1+ NC
IN2- GND
IN2+ NC
NC NC
NC CLK-
GND CLK+
NC NC
IN3- GND
IN3+ NC