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http://www.national.com

 

This  Evaluation  Board  is  configured  to  use  the  internal 
reference.  

 

4.3 ADC clock circuit 

Care must be taken to provide a high quality low jitter 
clock source. The board is configured to accept a single 
ended sinusoidal. It converts the sine wave to a 
differential signal through transformer T4. Refer to the 
schematic for more detail. 

4.4 Power Supply Connections 

Power is applied to the board through power connectors 
P1 – P4. Care must be taken to observe the correct 
polarity. 

 

5.0 Installing the ADC16DV160 Evaluation Board 

The  evaluation  board  requires  a  dual  power  supplies  as 
described  in 

Section  4.4

NOTE:  power  to  the 

WaveVision5  Data  Capture  Board  should  be  applied 
before  power  to  the  ADC16DV160  Evaluation  Board 
to  insure  that  the  FPGA  on  the  WaveVision5  Data 
Capture Board is not damaged. 

A low noise sinusoidal 

signal  source  should  be  connected  to  the  Clock  Input 
SMA connector  J4. An appropriate signal source should 
be  connected  to  the  Signal  Input  SMA  connector    J2. 
When  evaluating  dynamic  performance,  an  appropriate 
signal generator (such as R&S SMA-100A) with 50 Ohm 
source  impedance  should  be  connected  to  the  Analog 
Input connector through an appropriate bandpass filter as 
even the best signal generator available can not produce 
a  signal  pure  enough  to  evaluate  the  dynamic 
performance of an ADC. 

If this board is used in conjunction with the the 
WaveVision5™ Data Capture Board and WaveVision5™ 
software, a USB cable must be connected between the 
Data Capture Board and the host. See  the 
WaveVision5™ Data Capture Board  manual for details. 

  

Содержание ADC16DV160HFEB

Страница 1: ...1 http www national com National Semiconductor June 16 2010 Rev 1 0 ADC16DV160HFEB Evaluation Board User s Guide ADC16DV160 Dual 16 Bit 160 MSPS A D Converter 2009 National Semiconductor Corporation ...

Страница 2: ...ick Start 4 4 0 Functional Description 4 4 1 Analog Input 4 4 2 ADC reference circuitry 4 4 3 ADC clock circuit 5 4 4 Power Supply Connections 5 5 0 Installing the ADC16DV160 Evaluation Board 5 6 0 Hardware Schematic 6 7 0 Evaluation Board Layout 7 8 0 Evaluation Board Bill of Materials 10 ...

Страница 3: ...e captured data upon command and in addition to a frequency domain plot shows dynamic performance in the form of SNR SINAD THD SFDR and ENOB The latest WaveVision software is available through the National Semiconductor website http www national com analog adc wavevision5 2 0 Board Assembly The ADC16DV160 Evaluation Board comes pre assembled Refer to the Bill of Materials in Section 8 for a descri...

Страница 4: ...nnect a 160 MHz signal from a 50 Ohm source to connector J4 for the input Clock Be sure to use a bandpass filter before the Evaluation Board Set the amplitude to 18 dBm 4 Connect a signal from a 50 Ohm source to connector J2 I Channel or J3 Q Channel Be sure to use a bandpass filter before the Evaluation Board For best results also attach a 3dB 50 ohm attenuator right at the input SMA of the eval ...

Страница 5: ...applied before power to the ADC16DV160 Evaluation Board to insure that the FPGA on the WaveVision5 Data Capture Board is not damaged A low noise sinusoidal signal source should be connected to the Clock Input SMA connector J4 An appropriate signal source should be connected to the Signal Input SMA connector J2 When evaluating dynamic performance an appropriate signal generator such as R S SMA 100A...

Страница 6: ... B5 B5 B6 B6 B7 B7 B8 B8 B9 B9 B10 B10 B11 B11 B12 B12 B13 B13 B14 B14 B15 B15 B16 B16 B17 B17 B18 B18 B19 B19 B20 B20 B21 B21 B22 B22 B23 B23 B24 B24 C1 C1 C2 C2 C3 C3 C4 C4 C5 C5 C6 C6 C7 C7 C8 C8 C9 C9 C10 C10 C11 C11 C12 C12 C13 C13 C14 C14 C15 C15 C16 C16 C17 C17 C18 C18 C19 C19 C20 C20 C21 C21 C22 C22 C23 C23 C24 C24 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 D8 D8 D9 D9 D10 D10 D11 D11 D12 D...

Страница 7: ...7 http www national com 7 0 Evaluation Board Layout Layer 1 Component Side Layer 2 Ground ...

Страница 8: ...8 http www national com Layer 3 Power Layer 4 Ground Clock ...

Страница 9: ...9 http www national com Layer 5 Ground Layer 6 Circuit Side ...

Страница 10: ...D_TP1 GND_TP2 GND_TP3 TestPoint Keystone 5002 GND_TP4 GND2_TP1 GND2_TP2 17 1 NSC J1 Connector Future Bus Header96 Tyco Electronics 5223514 3 18 1 J2 INPUT_I Johnson 142 0701 851 19 1 J3 INPUT_Q Johnson 142 0701 851 20 1 J4 CLK_DIFF Johnson 142 0701 851 22 1 P1 VA3 0 Phoenix Contacts 1759017 23 1 P2 VA1 8 Phoenix Contacts 1759017 24 1 P3 VDR Phoenix Contacts 1759017 25 1 P4 VAD3 0 Phoenix Contacts ...

Страница 11: ... NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user 2 A critical componen...

Страница 12: ...for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agre...

Страница 13: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments ADC16DV160HFEB NOPB ...

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