Register Descriptions
Chapter 4
VXI-MXI User Manual
4-42
© National Instruments Corporation
When in Sync, Semi-Sync, or Async Source Mode, write a zero to
the PULSE bit in the Drive Triggers Register to generate a pulse
on the trigger line selected by the OTS[3-0] bits. You must write a
one to the PULSE bit before another pulse can be generated.
In Start-Stop Source Mode, write a zero to the PULSE bit in the
Drive Triggers Register to generate a Start signal on the trigger line
selected by the OTS[3-0] bits. Writing a one to the PULSE bit
generates a Stop signal.
When in the Semi-Sync Acceptor Mode, the ITS[3-0] bits select
the trigger line that the acceptor protocol is responding to. The
acceptor signal is driven onto the trigger line selected by the
OTS[3-0] bits. Write to the ASACK register to clear the acceptor
signal.
12-9w
ITS[3-0]
Input Trigger Select Bits
These bits select which VXIbus TTL or ECL trigger line is used to
generate the synchronous and asynchronous trigger interrupts.
ITS3
ITS2
ITS1
ITS0
Trigger Line
0
0
0
0
TTL Trigger Line 0
0
0
0
1
TTL Trigger Line 1
0
0
1
0
TTL Trigger Line 2
0
0
1
1
TTL Trigger Line 3
0
1
0
0
TTL Trigger Line 4
0
1
0
1
TTL Trigger Line 5
0
1
1
0
TTL Trigger Line 6
0
1
1
1
TTL Trigger Line 7
1
0
0
0
Reserved
1
0
0
1
ECL Trigger Line 0
1
0
1
0
ECL Trigger Line 1
1
0
1
1
Reserved
1
1
X
X
Reserved