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Glossary
VXI-AT2023/NI-VXI ISC 386/ix Getting Started
Glossary-2
© National Instruments Corporation
address window
A portion of address space that can be accessed from the application
program.
ANSI
American National Standards Institute
arbitration
A process in which a potential bus master gains control over a particular
bus.
asynchronous
Not synchronized; not controlled by time signals.
B
backplane
An assembly, typically a printed circuit board, with 96-pin connectors and
signal paths that bus the connector pins. A C-size VXIbus system will
have two sets of bused connectors called J1 and J2. A D-size VXIbus
system will have three sets of bused connectors called J1, J2, and J3.
binary
A numbering system with a base of 2.
block-mode
An uninterrupted transfer of data elements in which the master sources
transfer
only the first address at the beginning of the cycle. The slave is then
responsible for incrementing the address on subsequent transfers so that
the next element is transferred to or from the proper storage location. In
VME, the data transfer may have no more than 256 elements; MXI does
not have this restriction.
BTO
Bus Timeout Unit; a functional module that times the duration of each
data transfer and terminates the cycle if the duration is excessive. Without
the termination capability of this module, a bus master attempt to access a
nonexistent slave could result in an indefinitely long wait for a slave
response.
bus master
A device that is capable of requesting the Data Transfer Bus (DTB) for the
purpose of accessing a slave device.
C
C
Celsius
CLK10
A 10-MHz,
±
100-ppm, individually buffered (to each module slot),
differential ECL system clock that is sourced from Slot 0 and distributed
to Slots 1 through 12 on P2. It is distributed to each slot as a single-
source, single-destination signal with a matched delay of under 8 nsec.
CMOS
Complementary Metal Oxide Semiconductor; a process used in making
chips.
Commander
A Message-Based device which is also a bus master and can control one
or more Servants.