Chapter 3
NI SC Express Considerations
3-2
ni.com
On SC Express modules, the eight PXI trigger signals are synonymous with RTSI <0..7>. In
a PXI chassis with more than eight slots, the PXI trigger lines may be divided into multiple
independent buses. Refer to the documentation for your chassis for details.
PXI_STAR Trigger
In a PXI Express system, the Star Trigger bus implements a dedicated trigger line between
the system timing slot and the other peripheral slots. The Star Trigger can be used to
synchronize multiple modules or to share a common trigger signal among modules.
A system timing controller can be installed in the system timing slot to provide trigger signals
to other peripheral modules. Systems that do not require this functionality can install any
standard peripheral module in this system timing slot.
An SC Express module receives the Star Trigger signal (PXI_STAR) from a System timing
controller. PXI_STAR can be used as a trigger signal for input operations.
An SC Express module is not a System timing controller. An SC Express module can be used
in the system timing slot of a PXI system, but the system will not be able to use the Star
Trigger feature.
PXIe_DSTAR<A..C>
PXI Express devices can provide high-quality and high-frequency point-to-point connections
between each slot and a system timing slot. These connections come in the form of three
low-voltage differential star triggers that route between a PXI Express system timing
controller and a peripheral device. Using multiple connections simplifies the creation of
applications because of the increased routing capabilities.
Table 3-1 describes the three differential star (DSTAR) lines and how they are used.
Table 3-1.
PXIe_DSTAR Line Descriptions
Trigger Line
Purpose
PXIe_DSTARA
Distributes high-speed, high-quality clock signals from the system
timing slot to the peripherals (input).
PXIe_DSTARB
Distributes high-speed, high-quality trigger signals from the system
timing slot to the peripherals (input).
PXIe_DSTARC
Sends high-speed, high-quality trigger or clock signals from the
peripherals to the system timing slot (output).