Internal Real-Time Clock (RTC)
The system clock of the NI sbRIO device gets the date and time from the internal RTC at
startup. This synchronization provides timestamp data to the device.
Integrated 3.3 V Digital I/O
The NI sbRIO device provides 3.3 V output, 5 V tolerant input digital I/O via the 50-pin IDC
headers.
The following figure shows the circuitry of one 3.3 V DIO channel on the J4 or J5 IDC header.
Figure 23. Circuitry of One 3.3 V DIO Channel on the J4 or J5 IDC Header
ZYNQ 7020 FPGA
IDC Header
49.9
Ω
Bus
Switch
22
Ω
The NI sbRIO device is tested with all DIO channels driving ±3 mA DC loads. DIO signals
are tristated (floating) before and during FPGA configuration. After FPGA configuration
completes, unused DIO signals remain tristated. Refer to
3.3 V Digital I/O on 50-Pin IDC
Connector
section in the
NI sbRIO-9637 Specifications
on
ni.com/manuals
for the logic levels.
Integrated Analog Input
The sbRIO-9637 has 16 multiplexed, ±10 V, single-ended or eight differential, 16-bit AI
channels. Connector J5, the MIO connector, provides connections for analog inputs, outputs,
and grounds.
Figure 24. Single-Ended Analog Input
DIFF, RSE
I/O Connector
AI <0..15>
Mux
AI GND
PGIA
AI Terminal
Configuration
Selection
Input Range
Selection
ADC
AI Data
Analog Input Range
An input range is a set of input voltages that an analog input channel can digitize with the
specified accuracy. NI sbRIO devices with selectable input ranges have a programmable gain
NI sbRIO-9637 User Manual
|
© National Instruments
|
29
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
