frequency of the OCXO as needed, the 10 MHz PLL of the PXIe-6674T is able to match the
OCXO frequency to the reference clock supplied by the user from CLKIN.
Use of the 10 MHz PLL of the PXIe-6674T has advantages over using just CLKIN to drive
PXI_CLK10_IN:
•
Reference frequencies other than 10 MHz can be used. The 10 MHz PLL includes
internal dividers to divide both the reference from CLKIN and PXI_CLK10 down as
needed in order to make both a common frequency. This frequency is called the phase
detector frequency, as it is the frequency at which the PLL compares edge alignment to
determine if it should speed up or slow down the OCXO. NI-Sync allows any reference
frequency that is an integer multiple of 1 MHz to be used.
•
The 10 MHz PLL acts as a zero-delay buffer between the CLKIN SMA and PXI_CLK10/
PXIe_CLK100 at the backplane connector. Because the 10 MHz PLL uses PXI_CLK10
for feedback, it is able to create a known fixed phase relation between PXI_CLK10 and
the reference supplied on CLKIN. During manufacturing, the phase relation the 10 MHz
PLL maintains is adjusted so that a rising edge at the CLKIN SMA will align in time with
a rising edge of PXI_CLK10 at the peripheral slot connector of the backplane. This phase
relation will remain in place regardless of the PXI Express chassis used, allowing for
simpler multi-chassis system synchronization.
PXIe_DSTARA, PXIe_DSTARB, and PXIe_DSTARC
The PXI Express architecture includes a set of three high speed differential signal paths to
connect the system timing slot to each PXI Express peripheral slot (up to 17 peripheral slots).
These signals are PXIe_DSTARA, PXIe_DSTARB, and PXIe_DSTARC.
•
PXIe_DSTARA—PXIe_DSTARA is used to send clock signals from the system timing
slot to each PXI Express peripheral slot in a star configuration. PXIe_DSTARA uses
LVPECL signaling and closely matched trace lengths to achieve low skew, high speed
clock routing capabilities. Refer to
on page 17 for details on
how the PXIe-6674T implements PXIe_DSTARA.
•
PXIe_DSTARB—PXIe_DSTARB is used to send trigger signals from the system timing
slot to each PXI Express peripheral slot in a star configuration. PXIe_DSTARB uses
LVDS signaling and closely matched trace lengths to achieve faster, more precise
triggering than is achievable with PXI_STAR or PXI_TRIG.
•
PXIe_DSTARC—PXIe_DSTARC is used to send trigger signals from each PXI Express
peripheral slot to the system timing slot in a star configuration. PXIe_DSTARC uses
LVDS signaling and closely matched trace lengths and can be used to send a trigger
signal or clock signal to the system timing slot module. The PXIe-6674T receives each
PXIe_DSTARC signal and sends a copy to the PXIe_DSTARA network for clock sharing
and to the FPGA for trigger routing.
PXIe_DSTARA Network
To achieve the high speed, low skew routing performance required for PXIe_DSTARA, the
PXIe-6674T uses circuitry specifically designed for routing clock signals to
PXIe_DSTARA<0..16>. NI-Sync software automatically handles the routing through the
PXIe_DSTARA network. However because the PXIe_DSTARA Network limits the number of
PXIe-6674T User Manual
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© National Instruments
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