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frequency of the OCXO as needed, the 10 MHz PLL of the PXIe-6674T is able to match the
OCXO frequency to the reference clock supplied by the user from CLKIN.

Use of the 10 MHz PLL of the PXIe-6674T has advantages over using just CLKIN to drive
PXI_CLK10_IN:

Reference frequencies other than 10 MHz can be used. The 10 MHz PLL includes
internal dividers to divide both the reference from CLKIN and PXI_CLK10 down as
needed in order to make both a common frequency. This frequency is called the phase
detector frequency, as it is the frequency at which the PLL compares edge alignment to
determine if it should speed up or slow down the OCXO. NI-Sync allows any reference
frequency that is an integer multiple of 1 MHz to be used.

The 10 MHz PLL acts as a zero-delay buffer between the CLKIN SMA and PXI_CLK10/
PXIe_CLK100 at the backplane connector. Because the 10 MHz PLL uses PXI_CLK10
for feedback, it is able to create a known fixed phase relation between PXI_CLK10 and
the reference supplied on CLKIN. During manufacturing, the phase relation the 10 MHz
PLL maintains is adjusted so that a rising edge at the CLKIN SMA will align in time with
a rising edge of PXI_CLK10 at the peripheral slot connector of the backplane. This phase
relation will remain in place regardless of the PXI Express chassis used, allowing for
simpler multi-chassis system synchronization.

PXIe_DSTARA, PXIe_DSTARB, and PXIe_DSTARC

The PXI Express architecture includes a set of three high speed differential signal paths to
connect the system timing slot to each PXI Express peripheral slot (up to 17 peripheral slots).
These signals are PXIe_DSTARA, PXIe_DSTARB, and PXIe_DSTARC.

PXIe_DSTARA—PXIe_DSTARA is used to send clock signals from the system timing
slot to each PXI Express peripheral slot in a star configuration. PXIe_DSTARA uses
LVPECL signaling and closely matched trace lengths to achieve low skew, high speed
clock routing capabilities. Refer to 

PXIe_DSTARA Network

 on page 17 for details on

how the PXIe-6674T implements PXIe_DSTARA.

PXIe_DSTARB—PXIe_DSTARB is used to send trigger signals from the system timing
slot to each PXI Express peripheral slot in a star configuration. PXIe_DSTARB uses
LVDS signaling and closely matched trace lengths to achieve faster, more precise
triggering than is achievable with PXI_STAR or PXI_TRIG.

PXIe_DSTARC—PXIe_DSTARC is used to send trigger signals from each PXI Express
peripheral slot to the system timing slot in a star configuration. PXIe_DSTARC uses
LVDS signaling and closely matched trace lengths and can be used to send a trigger
signal or clock signal to the system timing slot module. The PXIe-6674T receives each
PXIe_DSTARC signal and sends a copy to the PXIe_DSTARA network for clock sharing
and to the FPGA for trigger routing.

PXIe_DSTARA Network

To achieve the high speed, low skew routing performance required for PXIe_DSTARA, the
PXIe-6674T uses circuitry specifically designed for routing clock signals to
PXIe_DSTARA<0..16>. NI-Sync software automatically handles the routing through the
PXIe_DSTARA network. However because the PXIe_DSTARA Network limits the number of

PXIe-6674T User Manual

  | 

© National Instruments

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17

Содержание PXIe-6674T

Страница 1: ...as follows Measurement hardware documentation This documentation contains detailed information about the measurement hardware that plugs into or is connected to the computer Use this documentation fo...

Страница 2: ...ompliance Information 36 WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS 36 Introduction The PXIe 6674T timing and synchronization module enables you to share clocks and triggers between module...

Страница 3: ...CVI is a complete ANSI C ADE that features an interactive video interface code generation tools and the LabWindows CVI Data Acquisition and Easy I O libraries Safety Information The following section...

Страница 4: ...y occur in electrical distribution systems The following is a description of measurement categories Measurement Category I is for measurements performed on circuits not directly connected to the elect...

Страница 5: ...ng software packages and documentation LabVIEW LabWindows CVI Microsoft Visual C MSVC PXI EMC filler panels National Instruments part number 778700 01 PXI Express chassis PXI Express embedded controll...

Страница 6: ...fully insert the module into the chassis 6 Screw the front panel of the device to the front panel mounting rail of the chassis 7 If adjacent slots are not populated use EMC filler panels to cover the...

Страница 7: ...erview This chapter presents an overview of the hardware functions of the PXIe 6674T Refer to Figure 2 on page 8 for a functional overview of the PXIe 6674T hardware PXIe 6674T User Manual National In...

Страница 8: ...ng PXI Express PXIe_CLK100 PXIe_DSTARA 0 16 OCXO CLK10 CLK100 PXIe_DSTARC 0 16 PXIe_DSTARB 0 16 PFI 0 Threshold DAC PFI 0 Driver Comparator Driver Comparator PFI 1 Threshold DAC LVDS Driver Receiver P...

Страница 9: ...PFI 4 LVDS 2 CLK OUT CLK IN 1 Access LED 2 Active LED 3 CLKOUT Connector 4 PFI 0 5 Connectors 5 CLKIN Connector Access LED The Access LED indicates the communication status of the PXIe 6674T Refer to...

Страница 10: ...ting If applicable check that the chassis fan air intake is not blocked and that the fan filters are clean Make sure that the ambient temperature around the chassis isn t above the rated temperature s...

Страница 11: ...able Function Interface which can be individually configured for either single ended operation or LVDS operation In LVDS mode the connectors are paired and can be programmatically set as either inputs...

Страница 12: ...OCXO is an extremely stable and accurate frequency source CLKIN In from front panel CLKIN is the signal connected to the SMA input connector of the same name CLKIN can be routed directly to PXI_CLK10_...

Страница 13: ...signals to and from these lines Note PXI_TRIG 0 5 are also known as RTSI 0 5 in some hardware devices and APIs However PXI_TRIG 6 7 are not identical to RTSI 6 7 PXI_STAR 0 16 In Out to from chassis T...

Страница 14: ...in advanced clock generation circuitry for generating clock signals from below 1 Hz to 1 GHz with very fine frequency resolution The clock generation circuitry is based on a direct digital synthesis D...

Страница 15: ...re has the advantage the PXI_CLK10 and PXIe_CLK100 are always sourced from the same reference oscillator and therefore it is impossible to lose PXI_CLK10 or PXIe_CLK100 by disconnecting the reference...

Страница 16: ...by using the CLKIN SMA on the front panel CLKIN is an AC coupled 50 terminated input to the PXIe 6674T In order to increase the amplitude of signals the CLKIN receiver can use the CLKIN circuitry fea...

Страница 17: ...al signal paths to connect the system timing slot to each PXI Express peripheral slot up to 17 peripheral slots These signals are PXIe_DSTARA PXIe_DSTARB and PXIe_DSTARC PXIe_DSTARA PXIe_DSTARA is use...

Страница 18: ...ork divides the 17 PXIe_DSTARA lines into four banks as shown in Table 5 on page 18 Table 5 PXIe_DSTARA Divisions Bank 0 Bank 1 Bank 2 Bank 3 PXIe_DSTARA 0 3 PXIe_DSTARA 4 7 PXIe_DSTARA 8 11 PXIe_DSTA...

Страница 19: ...FIs When enabled for LVDS operation the PFI_LVDS pair can be configured as either an input or an output PFI_LVDS lines can not be used as an input and output at the same time Because of the increased...

Страница 20: ...into a 50 load and is also AC coupled The sources available to be routed to CLKOUT differ depending on whether the low speed or high speed driver is used The sources available to the low speed driver...

Страница 21: ...tware Trigger are routed to SOURCE of each Selection Circuitry block SYNCHRONIZATION CLOCKS for PXI_STAR 0 16 PXI_TRIG 0 7 and PXIe DSTARB 0 16 Selection Circuitry Selection Circuitry Selection Circui...

Страница 22: ...outing operations must also define a third signal known as the synchronization clock Refer to the Choosing the Type of Routing section for more information on synchronous versus asynchronous routing F...

Страница 23: ...PFI inputs are programmable The input signal is generated by comparing the input voltage on the PFI connectors to the voltage output of software programmable DACs The thresholds for the PFI lines are...

Страница 24: ...vided by the second frequency divider 2m up to 512 Refer to Choosing the Type of Routing section for more information on the sychronization clock Note The PFI synchronization clock is the same for all...

Страница 25: ...Triggers The PXI triggers go to all the slots in the chassis All modules receive the same PXI triggers so PXI trigger 0 is the same for the system timing slot as it is for Slot 3 and so on This featur...

Страница 26: ...be matched to within 1 ns A typical upper limit for the skew in most NI PXI Express chassis is 500 ps The low skew of the PXI star trigger bus is useful for applications that require triggers to arriv...

Страница 27: ...ady logic high or low Backplane synchronization clock Refer to the Using the PXI Triggers section for more information on the backplane synchronization clock Choosing the Type of Routing The PXIe 6674...

Страница 28: ...chronous routing operation on the PXIe 6674T can be any of the following lines Any front panel PFI pin PFI 0 5 as single ended Any front panel PFI pin as LVDS PFI_LVDS 0 2 Any PXI star trigger line PX...

Страница 29: ...or example PXI_CLK10 all receiving devices can act on the trigger at the same time as shown in Figure 10 on page 29 Figure 10 Synchronous Routing to Multiple Destinations PXI_CLK10 Trigger Destination...

Страница 30: ...le methods to ensure this requirement is met go to ni com info and enter the Info Code SyncTriggerRouting Possible sources for synchronous routing with the PXIe 6674T include the following sources Any...

Страница 31: ...to an external reference clock the phase between the clocks can be adjusted The time between rising edges of PXI_CLK10 and the input clock is minimized using this constant Note The PXI_CLK10 phase is...

Страница 32: ...f the receiver the device suffering interference Relocate the transmitter the device generating interference with respect to the receiver Plug the transmitter into a different outlet so that the trans...

Страница 33: ...ace the product NI may use new or refurbished parts or products that are equivalent to new in performance and reliability and are at least functionally equivalent to the original part or product You m...

Страница 34: ...d Party Legal Notices You can find end user license agreements EULAs and third party legal notices in the following locations Notices are located in the National Instruments _Legal Information and Nat...

Страница 35: ...de dress Xilinx is the registered trademark of Xilinx Inc Taptite and Trilobular are registered trademarks of Research Engineering Manufacturing Inc FireWire is the registered trademark of Apple Inc L...

Страница 36: ...D TO DEATH PERSONAL INJURY SEVERE PROPERTY DAMAGE OR ENVIRONMENTAL HARM COLLECTIVELY HIGH RISK USES FURTHER PRUDENT STEPS MUST BE TAKEN TO PROTECT AGAINST FAILURES INCLUDING PROVIDING BACK UP AND SHUT...

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