the OCXO. This results in a reference oscillator that is several orders of magnitude more stable
and accurate than regular crystal oscillators.
Because the OCXO must warm up to a higher temperature than the ambient temperature
around it, there is a warm up time required to achieve the specified frequency accuracy. For
this reason, to achieve the most stable operation of the OCXO it is desirable to avoid powering
off the OCXO.
The OCXO used by the PXIe-6674T features electronic frequency control. This allows the
OCXO to be fine-tuned by varying the control voltage to the OCXO. The PXIe-6674T uses a
16-bit digital analog converter to give precise control of the tuning voltage. While the tuning
voltage can be varied by the user, it is normally controlled automatically by software, which
sets it to the calibration tuning voltage. The PXIe-6674T is calibrated during the
manufacturing process and should be recalibrated annually to remove frequency error that
accumulates over time (such as crystal aging). Refer to the PXIe-6674T Calibration Procedure
at
ni.com/calibration
for more details.
The OCXO can also be routed to the CLKOUT SMA and be used as a trigger synchronization
clock inside the FPGA.
CLKIN
The PXIe-6674T allows the user to connect their own 10 MHz reference directly to
PXI_CLK10_IN by using the CLKIN SMA on the front panel. CLKIN is an AC coupled, 50
Ω terminated input to the PXIe-6674T. In order to increase the amplitude of signals the
CLKIN receiver can use, the CLKIN circuitry features software enabled attenuation, which
will attenuate the input signal by a factor of five when enabled. NI-Sync software will by
default configure the attenuation to be enabled. If the input signal supplied to CLKIN is less
than 1.2 V
pp
, the attenuation should be turned off in order to extend down the range of
amplitudes CLKIN can receive.
When using CLKIN for driving PXI_CLK10_IN, please refer to the user manual for your PXI
Express chassis for information on the frequency range your chassis is capable of receiving on
PXI_CLK10_IN.
CLKIN can also be routed to the DSTARA network and be used as a trigger synchronization
clock inside the FPGA.
10 MHz PLL
The PXIe-6674T features a phase locked loop (PLL) circuit for aligning the frequency of the
OCXO with a reference clock supplied by the user from CLKIN. In this configuration, the
OCXO is routed to the backplane on PXI_CLK10_IN. The PXI Express backplane will in turn
phase lock the PXI_CLK10 and PXIe_CLK10 signal to the PXI_CLK10_IN signal. The
PXIe-6674T uses the PXI_CLK10 signal it receives from the backplane as feedback to the 10
MHz PLL circuitry. The PLL circuitry controls the frequency of the OCXO by varying the
tuning voltage used for electronic frequency control. By increasing or decreasing the
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ni.com
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PXIe-6674T User Manual
