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National Instruments PXIe-6594, Руководство по началу работы

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Signal

Type

Direction

 

 

 

MGT Tx± <0..3>

Xilinx Ult GTY

Output

MGT Rx± <0..3>

Xilinx Ult GTY

Input

DIO <0..7>

Single-ended

Bidirectional

5.0 V

DC

Output

GND

Ground

—

Figure 4. QSFP+ Connector Pinout

19

18

17

16

15

14

13

12

11

29

10

20

21

22

23

24

25

26

27

28

9

8

7

6

5

4

3

2

1

30

31

32

33

34

35

36

37

38

GND

Rx2n

Rx2p

GND

Rx4n

Rx4p

ModPrsL

GND

IntL

Vcc Tx

Vcc1

LPMode

GND

Tx3p

Tx3n

GND

Tx1p

Tx1n

GND

GND

Rx1n

Rx1p

GND

Rx3n

Rx3p

SDA

GND

SCL

Vcc Rx

ResetL

ModSelL

GND

Tx4p

Rx4n

GND

Tx2p

Tx2n

GND

The following table lists the available pins on the QSFP+ connectors.

Symbol

Signal Name

 

 

Txn

Transmitter Inverted Data Input

Txp

Transmitter Non-Inverted Data Input

Rxn

Receiver Inverted Data Output

Rxp

Receiver Non-Inverted Data Output

8

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ni.com

  | 

PXIe-6594 Getting Started Guide

Содержание PXIe-6594

Страница 1: ...rchangeable on the PXIe 6594 Contents FlexRIO Documentation and Resources 2 Verifying the System Requirements 2 Unpacking the Kit 3 PXIe 6594 Kit Contents 3 Preparing the Environment 3 Installing the...

Страница 2: ...unctionality of the LabVIEW FPGA Module FlexRIO Help Available at ni com manuals Contains information about the FPGA module front panel connectors and I O programming instructions and I O component le...

Страница 3: ...The following items are included in the device kit PXIe 6594 Documentation PXIe 6594 Getting Started Guide this document PXIe 6594 Safety Environmental and Regulatory Information Preparing the Enviro...

Страница 4: ...ation handle the module using the edges or the metal bracket 1 Ensure the AC power source is connected to the chassis before installing the module The AC power cord grounds the chassis and protects it...

Страница 5: ...1075 1 1 Chassis 2 Hardware Module 3 Ejector Handle in Downward Unlatched Position 9 Latch the module in place by pulling up on the ejector handle 10 Secure the module front panel to the chassis using...

Страница 6: ...anel and Pinout PXIe 6594 FlexRIO Serial Digital DIO 28 2 Gbps REF CLK IN CLK OUT 4 Vpp MAX PORT 0 PORT 1 The following table describes the signal connections for the PXIe 6594 6 ni com PXIe 6594 Gett...

Страница 7: ...ence Clock Figure 3 Digital I O Connector Pinout A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 R...

Страница 8: ...3 34 35 36 37 38 GND Rx2n Rx2p GND Rx4n Rx4p ModPrsL GND IntL Vcc Tx Vcc1 LPMode GND Tx3p Tx3n GND Tx1p Tx1n GND GND Rx1n Rx1p GND Rx3n Rx3p SDA GND SCL Vcc Rx ResetL ModSelL GND Tx4p Rx4n GND Tx2p Tx...

Страница 9: ...expand Devices and Interfaces to see the list of installed NI hardware Installed modules appear under the name of their associated chassis 3 Expand your Chassis tree item MAX lists all modules instal...

Страница 10: ...put and Output FlexRIO Click on an example and refer to the Information window for a description of the example Refer the Requirements window for a list of hardware that can run the example You can al...

Страница 11: ...k 1 12 V I O Module Mezzanine Connector DIO Connector Flash Power Supplies 12 V 3 3 V PXIe Backplane Module Clocking MGTs Configuration GPIO 1 8 V 5 V DStarB DStarC PXI Triggers PXIe_CLK100 PXI_CLK10...

Страница 12: ...operty CLIP for HDL IP integration FlexRIO devices support two types of CLIP user defined and socketed User defined CLIP allows you to insert HDL IP into an FPGA target enabling VHDL code to communica...

Страница 13: ...ify the PXIe 6594 appears in the Device Manager a Under the NI RIO Devices section confirm that a PXIe 6594 entry appears Note Device Manager identifies the PXIe 6594 as NI FlexRIO PXIe Module KU15P N...

Страница 14: ...as 78759 3504 USA For up to date contact information for your location visit ni com contact Information is subject to change without notice Refer to the NI Trademarks and Logo Guidelines at ni com tra...

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