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Chapter 2

Using the Module

sync pulse before the start trigger can be correctly handled in time. Step 6 in the 

Reference Clock 

Synchronization

 section allows NI-DAQmx to handle this delay automatically. After the digital 

start trigger, you cannot read data for the first sample in software until the digital filter group 
delay has elapsed. Therefore, it takes a total of twice the digital filter group delay to start an 
acquisition. You can insert additional time between when the sync pulse occurs and when the 
start trigger occurs. This will not affect the time it takes before samples are available after the 
start trigger, which is always the group delay time. Group delay time increases as sample rates 
decrease. Refer to the 

NI PXIe-4340 Device Specifications

 document for details regarding the 

group delay at different sample rates.

Synchronization

Some applications require tight synchronization between input and output operations on 
multiple modules. Synchronization is important to minimize skew between channels and to 
eliminate clock drift between modules in long-duration operations. You can synchronize the 
analog input operations on two or more PXIe-4340 modules to extend the channel count for your 
measurements. In addition, the PXIe-4340 can synchronize with other product families using 
Reference Clock Synchronization.

Reference Clock Synchronization

With Reference Clock Synchronization, master and slave modules generate their ADC 
oversample clock from the shared 100 MHz reference clock from the PXI Express backplane 
(PXIe_CLK100). The backplane supplies an identical copy of this clock to each peripheral slot. 
 In addition, multiple chassis can be synchronized by using a timing and synchronization board 
to lock the 100 MHz clock across chassis.

When you acquire data from multiple modules within the same NI-DAQmx task, NI-DAQmx 
will automatically handle all of the Reference Clock Synchronization details required to 
synchronize the modules within the task. This is known as a Multi-Device Task.

To perform Reference Clock Synchronization when using multiple NI-DAQmx tasks that are 
acquiring at the same rate, complete the following steps to synchronize the hardware.
1.

Specify PXIe_CLK100 as the reference clock source for all modules to force all the 
modules to lock to the reference clock on the PXI Express chassis.

2.

Choose an arbitrary PXIe-4340 master module to issue a sync pulse on one of the PXIe 
Trigger lines. The sync pulse resets the ADCs and oversample clocks, phase aligning all the 
clocks in the system to within nanoseconds.

3.

Configure the rest of the modules in your system to receive their sync pulse from the sync 
pulse master module. This will ensure all ADCs are running in lockstep.

4.

Choose one module to be the start trigger master. This does not have to be the same module 
you chose in step 2.

5.

Configure the rest of the modules in your system to receive their start trigger from the start 
trigger master module. This ensures that all modules will begin returning data on the same 
sample.

Содержание PXIe-4340

Страница 1: ...SC Express NI PXIe 4340 User Manual 4 Ch 24 bit 25 6 kS s Simultaneous AC LVDT Input Module NI PXIe 4340 User Manual May 2016 377014A 01...

Страница 2: ...mail addresses and current events National Instruments Corporate Headquarters 11500 North Mopac Expressway Austin Texas 78759 3504 USA Tel 866 ASK MYNI 275 6964 For further support information refer t...

Страница 3: ...ESS FOR A PARTICULAR PURPOSE TITLE OR NON INFRINGEMENT AND ANY WARRANTIES THAT MAY ARISE FROM USAGE OF TRADE OR COURSE OF DEALING NI DOES NOT WARRANT GUARANTEE OR MAKE ANY REPRESENTATIONS REGARDING TH...

Страница 4: ...es independent from National Instruments and have no agency partnership or joint venture relationship with National Instruments Patents For patents covering National Instruments products technology re...

Страница 5: ...ion 2 10 Overcurrent Detection 2 11 Signal Acquisition Considerations 2 11 Excitation Verification 2 11 Demodulation 2 11 ADC 2 11 Operation Modes 2 11 Buffered Mode Acquisitions 2 12 Buffered Mode Fi...

Страница 6: ...igure 2 3 4 Wire Connection to an LVDT or RVDT 2 5 Figure 2 4 5 Wire Connection to an LVDT or RVDT 2 5 Figure 2 5 6 Wire Connection to an LVDT or RVDT 2 5 Figure 2 6 Resolver Connections 2 6 Figure 2...

Страница 7: ...User Guide and Terminal Block Specifications document for step by step software and hardware installation instructions Note For a complete list of terminal blocks supported by a specific release of NI...

Страница 8: ...lable on the version specific download page or installation media Caution To ensure the specified EMC performance operate this product only with shielded cables and shielded accessories Use only twist...

Страница 9: ...t signal is zero If the core moves to the left the left secondary is more strongly coupled to the primary than the right secondary resulting in a stronger induced voltage in the left secondary and an...

Страница 10: ...ocations with Resulting Induced Voltage and Phase Secondary Primary Secondary Output Signal Core EOUT EIN EIN EIN EOUT EOUT Core at Center Secondary Primary Secondary Output Signal Core Core Left of C...

Страница 11: ...three secondaries stators that produce three simultaneous signals proportional to the sine of the shaft position each offset by 120 Therefore synchros can measure over 360 of rotation with a unique c...

Страница 12: ...ection to an LVDT or RVDT Figure 2 4 5 Wire Connection to an LVDT or RVDT Figure 2 5 6 Wire Connection to an LVDT or RVDT Note The PXIe 4340 does not require connection to the center tap of 5 and 6 wi...

Страница 13: ...e to guarantee accuracy Figure 2 6 Resolver Connections Connecting Synchro Signals This section provides information regarding connecting synchro signals Figure 2 7 shows the connections made between...

Страница 14: ...of the excitation source and adjusts its amplitude against an internal reference The PXIe 4340 does not support external adjustment Module Pinout Table 2 1 shows the pinout of the front connector of t...

Страница 15: ...27 NC NC NC 26 AIGND EX1 AI1 25 NC EX1 AI1 24 NC RS1 RS1 23 NC NC NC 22 NC NC NC 21 NC NC NC 20 NC NC NC 19 NC NC NC 18 NC NC NC 17 NC NC NC 16 NC NC NC 15 NC NC NC 14 AIGND EX2 AI2 13 NC EX2 AI2 12 N...

Страница 16: ...irection Description AIGND Analog Input Ground AI 0 3 Input Positive inputs of the differential analog input channels 0 to 3 AI 0 3 Input Negative inputs of the differential analog input channels 0 to...

Страница 17: ...tects the increase in voltage and reports this condition to software The PXIe 4340 also senses the impedance connected to the excitation lines and reports a high impedance connection to Digital Sine G...

Страница 18: ...age measured because the higher impedance is more sensitive to loading from the verification instrument Demodulation The PXIe 4340 digitizes oversampled data which is digitally demodulated The digital...

Страница 19: ...in addition to the filtering provided by the demodulator This means that the digital filter bandwidth increases until reaching the full bandwidth of the demodulation filter where it stops increasing...

Страница 20: ...nally generated on the PXIe 4340 using the sample rate configured with a NI DAQmx task During Buffered acquisitions the device may wait to transfer data to the host machine to build larger bus transac...

Страница 21: ...k signal Maximum HWTSP Rate Analysis During HWTSP acquisitions the maximum achievable acquisition rate without missing a sample is affected by both the transfer and application time Refer to Figure 2...

Страница 22: ...e is acquired and the time the AO stimulus is generated is 500 s Refer to Figure 2 12 Figure 2 12 Input and Output of a Control System with Bandwidth 2 kHz To make sure that your application can run a...

Страница 23: ...the application time or by using an excitation frequency in a faster demodulation latency range Timing and Triggering This section contains information about timing and triggering Sample Clock Timebas...

Страница 24: ...tart trigger This restriction is a result of the way the module compensates for the filter group delay When using an analog reference trigger the module first waits for the specified number of pre tri...

Страница 25: ...and slave modules generate their ADC oversample clock from the shared 100 MHz reference clock from the PXI Express backplane PXIe_CLK100 The backplane supplies an identical copy of this clock to each...

Страница 26: ...find example VIs in the NI Example Finder Select Help Find Examples to launch the NI Example Finder Consider the following caveat to using Reference Clock Synchronization The PXIe 4340 automatically...

Страница 27: ...vide power to the accessories as well as digital communication lines This allows software to detect when accessories are inserted or removed In addition software can automatically identify the specifi...

Страница 28: ...eral slot in a PXI Express chassis PXIe_SYNC100 allows modules using PXIe_CLK100 as their reference to recreate the timing of the PXI_CLK10 signal while taking advantage of the lower skew of PXIe_CLK1...

Страница 29: ...slot of a PXI system but the system will not be able to use the Star Trigger feature PXIe_DSTAR A C PXI Express devices can provide high quality and high frequency point to point connections between...

Страница 30: ...fy your systems accuracy and reliability requirements and provides warranty sparing and calibration services to help you maintain accuracy and minimize downtime over the life of your system Visit ni c...

Страница 31: ...tions Engineers make sure every question submitted online receives an answer Software Support Service Membership The Standard Service Program SSP is a renewable one year subscription included with alm...

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