© National Instruments
|
1-9
NI PXIe-1085 Series User Manual
Figure 1-4.
NI PXIe-1085 24 GB/s PCI Express Backplane Diagram
System Timing Slot
The System Timing Slot is slot 10. The system timing slot will accept the following peripheral
modules:
•
NI PXIe-1085 12 GB/s—
A PXI Express System Timing Module with x8, x4, or x1
PCI Express link to the system slot through a PCI Express switch. Each PXI Express
peripheral slot can link up to a Gen-2 x8 PCI Express, providing a maximum nominal
single-direction bandwidth of 4 GB/s.
•
NI PXIe-1085 24 GB/s—
A PXI Express System Timing Module with x8, x4, or x1
PCI Express link to the system slot through a PCI Express switch. Each PXI Express
peripheral slot can link up to a Gen-3 x8 PCI Express, providing a maximum nominal
single-direction bandwidth of 8 GB/s.
•
A PXI Express Peripheral with x8, x4, or x1 PCI Express link to the system slot through a
PCI Express switch.
•
A CompactPCI Express Type-2 Peripheral with x8, x4, or x1 PCI Express link to the system
slot through a PCI Express switch.
The system timing slot has 3 dedicated differential pairs (PXIe_DSTAR) connected from the
TP1 and TP2 connectors to the XP3 connector for each PXI Express hybrid peripheral slot, as
well as routed back to the XP3 connector of the system timing slot as shown in Figure 1-5. The
PXIe_DSTAR pairs can be used for high-speed triggering, synchronization and clocking. Refer
to the
PXI Express Specification
for details.
The system timing slot also has a single-ended (PXI Star) trigger connected to every slot. Refer
to Figure 1-5 for details.
The system timing slot has a pin (PXI_CLK10_IN) through which a system timing module may
source a 10 MHz clock to which the backplane will phase-lock. Refer to the
System Reference
Clock
section for details.
x
8
x1
x
8
x16
3
H
2
H
4
H
5
H
6
H
7
H
8
H
9
H
11
H
12
H
1
3
H
14
H
15
H
16
H
17
H
1
8
H
Gen-
3
PCIe
S
witch 1
Port 16 Port 17 Port 20 Port 21
Gen-
3
PCIe
S
witch 2
10
1
PCI B
us
1
PCI B
us
2
Po
rt
0
P
o
rt
8
Po
rt
9
Port 17 Port 20 Port 21
P
o
rt
4
P
or
t 5
P
or
t 1
2
P
o
rt
1
3
Port 16
Po
rt
1
2
Po
rt 9
Po
rt
8
Po
rt 1
Po
rt 0
P
o
rt 1
3
P
o
rt 4
P
ort 5
x
8
x
8
x
8
x
8
x
8
x
8
x
8
x
8
x
8
x
8
x
8
x
8
x
8
x
8
x
8
Brdg
Brdg
x
8
x1
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