Chapter 1
Getting Started
1-6
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System Reference Clock
The PXI-1025 MegaPAC supplies the PXI 10 MHz system clock signal
(PXI_CLK10) independently to each peripheral slot. An independent
buffer (having a source impedance matched to the backplane and a skew
of less than 1 ns between slots) drives the clock signal to each peripheral
slot. You can use this common reference clock signal to synchronize
multiple modules in a measurement or control system. You can drive
PXI_CLK10 from an external source through the PXI_CLK10_IN pin
on the P2 connector of the Star Trigger Slot. (See Table B-4,
Connector Pinout for the Star Trigger Slot
Sourcing an external clock on this pin automatically disables the
backplane’s 10 MHz source.
