Component-Level Intellectual Property (CLIP)
The LabVIEW FPGA Module includes component-level intellectual property (CLIP) for HDL
IP integration. FlexRIO devices support two types of CLIP: user-defined and socketed.
•
User-defined CLIP
allows you to insert HDL IP into an FPGA target, enabling VHDL
code to communicate directly with an FPGA VI.
•
Socketed CLIP
provides the same IP integration of the user-defined CLIP, but it also
allows the CLIP to communicate directly with circuitry external to the FPGA. Adapter
module socketed CLIP allows your IP to communicate directly with both the FPGA VI
and the external adapter module connector interface.
The PCIe-5775 ships with socketed CLIP items that add module I/O to the LabVIEW project.
Making a Measurement with LabVIEW
1.
Launch LabVIEW.
2.
Select
Help
»
Find Example
.
3.
Open the example VI that you want to use by selecting
Hardware Input and Output
»
FlexRIO
.
4.
Follow any setup, configuration, and execution instructions in the VI.
Synchronization
You can use the compact synchronization interface cable (part number 769693-01) to share a
Reference Clock and triggers between the PCIe-5775 and another PCI Express FlexRIO
device. You also can use the compact synchronization interface to RTSI adapter (part number
147008A-01L) to synchronize the PCIe-5775 with a PCI Express device that supports
synchronization using RTSI.
PCIe-5775 Getting Started Guide
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© National Instruments
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